EEVblog #635 - FPGA's Vs Microcontrollers

[EEVblog]

How easy are FPGA's to hook up and use use compared to traditional microcontrollers?

A brief explanation of why FPGA are a lot more complicated to setup and get working that microcontrollers.
A short video linking to several other FGPA videos.
NOTE: This is very old footage that was meant to be part of a series of videos on trying out some FPGA demo boards. It's been sitting around for too long, so I'm uploading all the footage I have now.

[mux]

What I find so baffling (well, until recently) is that often I'd really like to use an FPGA in a project because I need to do something that just won't work on a simple microcontroller... but the darn things are so incredibly expensive and complicated to set up that it's just not worth it. Minimum price to entry used to be a solid $20 BOM, even for the simplest devices. I often had bus timing or synchronization stuff that I'd wanted to do in an FPGA but in the end I'd just use an ARM microcontroller because it was at least an order of magnitude cheaper - as well as 1000x easier to program for. FPGAs are so incredibly niche!

Now, this has gotten somewhat better with the recent lattice FPGAs. The ICE40s are essentially about the price of a high-end µC and pretty easy to develop for as well. And at least for my applications the amount of logic in them is sufficient with a bit of optimization on the board level and mucking about with what the micro does besides the FPGA.

I just don't get why you would ever want to put a soft core into an FPGA, or anything else than the absolute bare minimum necessary so you can buy the cheapest skew. Even going up one skew on an ICE40 costs me more than €1.50, for which I can buy two cortex-M0's. Let alone those beasts that cost $40+ just for the chip!

[mikeselectricstuff]

Lattice XO2 devices mop up a lot of this messy stuff - internal core voltage regulator, flash and even an oscillator, albeit with only 5% accuracy.

..and does anyone use platform flash these days now that SPI flash is so cheap?
You can in most cases program it through the FPGA, avoiding the need to have seperate connections to the programmer.

I really don't understand why FPGAs don't include at least an MCU style osc that you can connect a crystal to.

[jahonen]

I really don't understand why FPGAs don't include at least an MCU style osc that you can connect a crystal to.

Besides Altera FPGAs already have one oscillator already built in, the 30 MHz (depends on device type) or so one that clocks the configuration from EPCS device, so why not make use of that?

Regards,
Janne

[EEVblog]

Besides Altera FPGAs already have one oscillator already built in, the 30 MHz (depends on device type) or so one that clocks the configuration from EPCS device, so why not make use of that?

Yes, I've never understood why it's not accessible in the timing fabric?

[FrankBuss]

It is possible to use the internal Cyclone clock:

http://www.alteraforum.com/forum/showthread.php?t=36010

Might be all you need for some simple applications, like a blinking LED, even RS232 should work with an auto-baud detection, but much easier to have a more accurate external clock.

[Kjelt]

I think FPGA's are a bridge too far for hobbieists, they usually are extremely large and expensive and used for prototyping large circuits such as video circuits and such.
Nice for companies and pro's but not for amateurs.

For electronic hobbieists a device with 500 to 2000 gates or so easy setup, free IDE etc. would be a nice product.
I have looked ten years ago at CPLDs, but still you needed the same huge software suite to get going with them.

About 12 years ago in the Elektor magazine they talked about a chip that would replace the entire HEF4000/74HC series of ic's.
They would have all the possible gates in them and you would select through a GUI which input would connect through what gates to what output, some sort of universal next gen GAL/PAL logic series. Never heard of it anymore, has it come out or died at the drawing table? I saw that there are single logic gates at extremely small SMD packages but I am still waiting for such a small but generic gate product.

[FrankBuss]

About 12 years ago in the Elektor magazine they talked about a chip that would replace the entire HEF4000/74HC series of ic's.
They would have all the possible gates in them and you would select through a GUI which input would connect through what gates to what output, some sort of universal next gen GAL/PAL logic series. Never heard of it anymore, has it come out or died at the drawing table? I saw that there are single logic gates at extremely small SMD packages but I am still waiting for such a small but generic gate product.

You can use any small CPLD for it (except the CD4040 analog switch and other analog functions), like the Altera Max series or the Xilinx XC9500XL series. The small Xilinx parts costs EUR 2. It needs just one 3.3V supply voltage and has integrated flash (but you need an external JTAG programmer). For static logic you don't even need a clock. I used it for re-implementing the C64 PLA:

http://www.frank-buss.de/c64/pla/index.html

Such small CPLDs, or similar small FPGAs in TQFP, are well within the capabilities of advanced hobbieists these days.

[mikeselectricstuff]

I think FPGA's are a bridge too far for hobbieists, they usually are extremely large and expensive and used for prototyping large circuits such as video circuits and such.
Nice for companies and pro's but not for amateurs.

For electronic hobbieists a device with 500 to 2000 gates or so easy setup, free IDE etc. would be a nice product.
I have looked ten years ago at CPLDs, but still you needed the same huge software suite to get going with them.

Nonsense -there are plenty of small devices in useable packages and a ton of cheap devboards.
Given a particular package size, it is easier to develop on a larger device, as it will be less effort (i.e. quicker) to fit the design.
Although CPLDs are simpler, they are very limited in terms of registers, so the range of applications is somewhat limited. One upside is that compile time is much faster as there is minimal place/route. You typically still have to download a huge devtool though.
The main reason FPGAs aren't popular with hobbyists is simply that hobbyists don't often have applications that need them.   

[free_electron]

MY two cents :

Do NOT compare FPGA and microcontrollers. They are totally different beasts. Yes, you can plonk a softcore in the larger ones but those are only used to do stuff that is too complex to synthesize into hard logic. Apart from some very niche applications no sane system designers cams the entire logic + cpu in an FPGA. they are too expensive for that.

An FPGA (or CPLD ) is designed to get rid of the riff-raff of logic support chips you typically need in a system. Take a singleboard cpu system where you can;t find chips for your mix of IO
let's say i need 3 serial ports , 48 channels of 12 bit PWM , a pixel matrix LED driver ( 8 pixels high and 64 pixels wide ) a few SPI hosts running autonomously. 8 precision timers that can measure tie intervals. and a keyboard scanner for a 4x6 matrix.

Are you really going to plonk all that stuff on a board made with 8251 uarts , a bunch of 74xx logic , and other stuff that is built from lots of different xhips and requiring a lot fo software support from the CPU to keep it alive ? Drop in a small FPGA , you define your own register map , map into memory space of the CPU , and give the logic the intelligence needed.

That is where FPGA's are golden. They are to be used to extend to CPU. Extend it with smart functionality that , in discrete logic, would be a double eurocard in size.
And, if something pops up you didn;t think of : the darn thing is reprogrammable. so you can shorten your design cycle. Spit out the board first and while it is in fab you can code the FPGA logic.

[Kjelt]

Ok my bad, my personal definition of FPGA are the stratix devices with prices >$50 to $2000 a piece, very high in LE's and I think too expensive for a hobbieist.
The small cheap devices I call CPLD, they don't need an external memorydevice and startup right away, very suitable for hobbieists.

Anyway my point was that for a starter/hobbieist there is no easy device where you can download a free IDE/GUI on which you can design a digital schematic and compile and download to a CPLD target device costing <$3.-
All I see you need to know VHDL and that is a big hurdle for a beginner, it took me two courses and three weeks at work with colleagues to understand the basics and now ten years later I would not remember a single thing except that you had to pipeline the whole design otherwise you had a lot of problems with the timing  .

Maybe I am missing the latest developments in the market which I would really like to hear from you guys. I do see Lattice has inexpensive devices with a lot of LUTs that might be suitable.

[djacobow]

Haven't programmed an FPGA in about a decade. Was a little surprised to see that the Altera tool is still called "Quartus II." Would have thought they'd be on Quartus MCMLCCIV by now.

Anyway, it seems to me that the FPGA folks are designing their parts around some assumptions about the systems in which they're going to be deployed. There is nothing stopping them from adding "usability" features to cut down on external parts and hassle. The programming flash can be internal, they can have their own oscillators and PLLs, etc. Heck, if they have a hard core in them, they could put a bootloader that allows the core to configure the fabric from the same blob its downloading to run its code.

I suspect, though, that Xilinx/Altera have done their homework and determined that providing such "niceties" would waste silicon area on something that most customers (* volume) doesn't value. Of course, they could bring in zillions of hobbyists, but that does not drive volume. I also wonder how they would handle the reduced ratio of support calls to parts shipped. It's hard to imagine the average Arduino user dealing the timing closure, clock skew, etc.

 Two other random points:

1. part of the reason FPGAs are a bit harder to work with vis a vis voltages is that they tend to be on the bleeding edge of process technology. They sort of have to be to get their marketing numbers for density, speed, etc. And the latest submicron processes are not super-friendly to "high" voltages like 3.3V

2. Why have no uC vendors gotten into the act by putting a dash of FPGA fabric into their devices, to be made accessible as a memory-mapped peripheral? (Or have they?) That would be cool, I think, and would be kind of community-friendly where people could swap and sell "soft peripherals." People who don't want to design their own could skip the fancy tools and just add in magic blobs from a database. Could be great for "just one more timer" or a UART with a custom twist, etc. I could see this eating into the market for CPLDs and smaller FPGAs. Also, a way for one of the ARM core providers to get some lock in. Right now, from there perspective, it has to be too easy for designer to switch platforms without pain.

[FrankBuss]

Anyway my point was that for a starter/hobbieist there is no easy device where you can download a free IDE/GUI on which you can design a digital schematic and compile and download to a CPLD target device costing <$3.-

$2.26 CPLD: http://www.digikey.com/product-detail/en/XC9572XL-10VQG44C/122-1448-ND/966629
Xilinx ISE WebPACK Schematic Capture Tutorial (ISE WebPACK is free): http://www.digilentinc.com/Data/Documents/Tutorials/Xilinx%20ISE%20WebPACK%20Schematic%20Capture%20Tutorial.pdf
Personally I prefer VHDL, but it might be interesting for people who are more used to draw schematics than write programs.

[alter Ratz]

Hello Dave,

"Most beginners probably won't need wont need Modelsim" - I completely disagree. To understand really whats going on inside the FPGA the only way is simulation. You can have a look at every byte while you don't need to perform a new synthesis run for each change. A few years ago I was part in developing a large ASIC for the automotive industry. Most of our work was done in Simulation. Then tests on FPGA, followed by timed simulations from the ASIC model and last tests on the actual ASIC. Also it is much easier to genarate test stimuli using simulation than on FPGA and last but not least you can create test benches and automatically perform regression tests on using simulation, which can be used for both, the simple HDL model as well as the timed model from the ASIC design.

However, for projects like the VGA driver (which seems to be part of each undergraduate FPGA course), it is of course much more  satisfying to see something on the monitor than just a few waveforms on the monitor.

However, the problem with modelsim is that you cannot afford it     The version which comes with Quartus II is slowed down considerably in comparison to the full version and you cannot perform mixed mode simulation, which really sucks, for instance if you want to check out some cores from opencores.org and one is in VHDA and the other in Verilog.

However, I liked this video very much and it made me eager to do some little FPGA project myself again .....

Best  regards,
Bernhard

[Someone]

2. Why have no uC vendors gotten into the act by putting a dash of FPGA fabric into their devices, to be made accessible as a memory-mapped peripheral? (Or have they?)

Atmel tried that low end market:
http://www.digikey.com/catalog/EN/partgroup/fpslic/14188
But the compute/flexible capabilities of the FPGA ended up dominating the cost of the parts (combined with low volumes).

For electronic hobbieists a device with 500 to 2000 gates or so easy setup, free IDE etc. would be a nice product.

Then they'll complain how small it is and they can't put a soft core on in? FPGAs and CPLDs are available in densities from dozens of gates through to millions with a surprising granularity, there are several parts in the $5 range that would meet the 500-2000 gate size.

[darrell]

Besides Altera FPGAs already have one oscillator already built in, the 30 MHz (depends on device type) or so one that clocks the configuration from EPCS device, so why not make use of that?

Yes, I've never understood why it's not accessible in the timing fabric?

On Xilinx parts, the configuration clock is available after configuration. I have used it to get the real clock initialized.

[Kjelt]

$2.26 CPLD:
Xilinx ISE WebPACK Schematic Capture Tutorial
Personally I prefer VHDL, but it might be interesting for people who are more used to draw schematics than write programs.

Thanks, looks quite interesting. I agree that if you are serious or getting work-related you should definitely start to learn VHDL, it is just a very steep learning curve.

Then they'll complain how small it is and they can't put a soft core on in?  

You're  much better off (esp. for hobby) with a standalone microcontroller having its own RAM and flash then a softcore and having to allocate all those stuff ending up with a 95% full device. I totally agree with free_electron that the FPGA/CPLD should be used for tasks that a micro can not handle or has not enough resources for. Esp. doing digital interfacing with time critical tasks in the 5-500 ns domain.

[AlfBaz]

I find it a bit odd to be trying to entice "hobbyist's" to get involved in fpga's and in the same breath bad-mouthing the use of soft-cores within them.

Considering the vast and cheap number of fpga dev boards out there without dedicated mcu's it's almost a "must do" situation to embed a small soft core in them as part of the learning process.

You develop hardware on them and drive/control them with the softcore to test you development. A beginner well versed in mcu's is going to have a much easier time easing into hardware development by "offloading" complex functionality to a softcore whilst verifying their hdl code

[Rerouter]

Or do what i am about to embark on, grabbing my favorite FPGA dev board, a powerful micro dev board, and connecting the DMA interface on the micro direct to the fpga to have some fun, rather than doubling the price on the fpga to have a similar capacity hard core in the fpga, (arguabliy i have to use more pins, but for my projects i have never exceeded 50 I/O,

[alter Ratz]

2. Why have no uC vendors gotten into the act by putting a dash of FPGA fabric into their devices, to be made accessible as a memory-mapped peripheral?

I think the problem is that you could not implement anything like this without stumbling across 1000ands of patents. Try looking at the FPGA of your favorite development board for more than five minutes and you can be sure a    patent attorney is already standing next to you. Even if a FPGA is not much more than a bunch of EEPROM or FLASH lookup tables interconnected with a little bit of glue logic ...

Regards,
Bernhard

[mikeselectricstuff]

2. Why have no uC vendors gotten into the act by putting a dash of FPGA fabric into their devices, to be made accessible as a memory-mapped peripheral? (Or have they?) That would be cool, I think, and would be kind of community-friendly where people could swap and sell "soft peripherals." People who don't want to design their own could skip the fancy tools and just add in magic blobs from a database. Could be great for "just one more timer" or a UART with a custom twist, etc. I could see this eating into the market for CPLDs and smaller FPGAs. Also, a way for one of the ARM core providers to get some lock in. Right now, from there perspective, it has to be too easy for designer to switch platforms without pain.

The problem is how much FPGA do you put on there ?
Too  little & it's not useful, too much and the chip is too expensive and/or power hungry.
For high volume markets, it will be cheaper to put the exact peripherals you need on there, for lower volumes, just use seperate chips, each sized to the application.
Psoc is about the closest, where they effectively implement a lot of the peripherals as flexible logic, so you can trade them off between each other.

[ukee1593]

I remember discussing with a friend a while ago; wondering when someone was going to make the "Arduino of FPGAs" that is easy to build with and program with. 

It looks as though something like this (Say an FPGA with internal flash so you don't have volatility, internal oscillators, peripherals such as ADC, DACs, and in a DIP package would require an entirely new product line from Xilinx or Altera that would be very different from anything available now.  At the moment, the development boards that are currently available are as close as we are going to get with current silicon ... and producing something which the hobbyist/maker market would feel comfortable using would require a lot more work than what turning an AVR into an Arduino did. 

As for CPLDs, I've looked into these a couple of times when I have gotten lazy and didn't want to build something using 74 series logic, but I've always decided against it in the end as anything I've done with logic has been quite simple, and I've always gotten worried about the cost/effort of getting programmers and software for the devices (perhaps I'll watch Dave's JTAG video and see if that sheds any light on it).  However, surely there is a sizable amount of people who want a micro controller and a bit of discrete logic on the same board ... and building a micro+CPLD would be a good way of merging the two, and ensuring a standardized software platform for programming the CPLD? 

[mikeselectricstuff]

I remember discussing with a friend a while ago; wondering when someone was going to make the "Arduino of FPGAs" that is easy to build with and program with. 

Probably never, as you will always have to use the vendors place & route tools. You could make a nice front-end that called these & package it all up, but even if done really well it would still have a significant compile time.
This is where CPLD may be better, but probably too limiting.
 

Say an FPGA with internal flash so you don't have volatility, internal oscillators,

lattice XO2

peripherals such as ADC,

Doesn't make sense to put an ADC on an FPGA as everyone will want something different

DACs,

How many MCUs have a DAC?
An FPGA can easily do PWM or even delta-sigma with minimal external parts

and in a DIP package

Nobody wants enough parts in DIP to make it viable

  At the moment, the development boards that are currently available are as close as we are going to get with current silicon ...

And there is no real need to go any closer - if you want DIP, you don't care about size, so  a PCB with a header is fine.

and building a micro+CPLD would be a good way of merging the two, and ensuring a standardized software platform for programming the CPLD?

Lattice, and probably others, supply software to program FPGAs and CPLDs from an MCU.

[AlfBaz]

I remember discussing with a friend a while ago; wondering when someone was going to make the "Arduino of FPGAs" that is easy to build with and program with. 

Probably never, as you will always have to use the vendors place & route tools. You could make a nice front-end that called these & package it all up, but even if done really well it would still have a significant compile time.
This is where CPLD may be better, but probably too limiting.

Yeah, that front end thing worked out well for altium

[xygor]

On Xilinx parts, the configuration clock is available after configuration. I have used it to get the real clock initialized.

Which one(s)?  CCLK is supposed to go tristate shortly after configuration from an FPGA in master mode.  For slave mode, I am not sure what CCLK from a Xilinx configuration PROM does, but I think that stops too.

[xygor]

Does anyone remember or have used 'jbits'?
http://www.xilinx.com/prs_rls/end_markets/03108jbits.htm

It was withdrawn.  It looks like it would have allowed one to write one's own synthesis and P&R software.

[miguelvp]

There is Altera OpenCL
http://www.altera.com/products/software/opencl/opencl-index.html

For now it's aimed to Stratix V and up so a dev board will probably cost north of $5K

but it's a step in the right direction.

[BytesGuy]

Lattice XO2 devices mop up a lot of this messy stuff - internal core voltage regulator, flash and even an oscillator, albeit with only 5% accuracy.

..and does anyone use platform flash these days now that SPI flash is so cheap?
You can in most cases program it through the FPGA, avoiding the need to have seperate connections to the programmer.

I really don't understand why FPGAs don't include at least an MCU style osc that you can connect a crystal to.

Would you recommend one of those XO2 breakout boards as a cheap way to get into FPGAs?

I don't really fancy forking out £100+ on an FPGA board because I probably won't use it enough!

I do like the fact the breakout board gives you access to virtually every pin so you are not bound to use peripherals that are pre built on the board.

[mikeselectricstuff]

Lattice XO2 devices mop up a lot of this messy stuff - internal core voltage regulator, flash and even an oscillator, albeit with only 5% accuracy.

..and does anyone use platform flash these days now that SPI flash is so cheap?
You can in most cases program it through the FPGA, avoiding the need to have seperate connections to the programmer.

I really don't understand why FPGAs don't include at least an MCU style osc that you can connect a crystal to.

Would you recommend one of those XO2 breakout boards as a cheap way to get into FPGAs?

I don't really fancy forking out £100+ on an FPGA board because I probably won't use it enough!

I do like the fact the breakout board gives you access to virtually every pin so you are not bound to use peripherals that are pre built on the board.

Yes, definitely
http://uk.mouser.com/ProductDetail/Lattice/LCMXO2-7000HE-B-EVN/?qs=sGAEpiMZZMurtJ7VwBTl0fuXvMOPgNe8hSHI90CFJ0k%3d

[BytesGuy]

Lattice XO2 devices mop up a lot of this messy stuff - internal core voltage regulator, flash and even an oscillator, albeit with only 5% accuracy.

..and does anyone use platform flash these days now that SPI flash is so cheap?
You can in most cases program it through the FPGA, avoiding the need to have seperate connections to the programmer.

I really don't understand why FPGAs don't include at least an MCU style osc that you can connect a crystal to.

Would you recommend one of those XO2 breakout boards as a cheap way to get into FPGAs?

I don't really fancy forking out £100+ on an FPGA board because I probably won't use it enough!

I do like the fact the breakout board gives you access to virtually every pin so you are not bound to use peripherals that are pre built on the board.

Yes, definitely
http://uk.mouser.com/ProductDetail/Lattice/LCMXO2-7000HE-B-EVN/?qs=sGAEpiMZZMurtJ7VwBTl0fuXvMOPgNe8hSHI90CFJ0k%3d

Thanks Mike

£17 is a really good price. Shame the delivery is £12 though, know of any other places that may be cheaper?

[hamster_nz]

Would you recommend one of those XO2 breakout boards as a cheap way to get into FPGAs?

Any FPGA board will get you into FPGAs quicker than not having a board at all. But if you think about it for a while, does having a breakout board as your first dev board make sense?

To make use of FPGAs you are going to spend a while 'fiddling' with the technology. To do anything moderately complex will take a lot of study to develop the skills to make it work. It is worth it, as once over the hump in the learning curve almost anything is then possible.

So when you buy your first FPGA board, don't think "goodie! this is the board that I am going to use to build a SDR platform or 100 MHz 32-bit CPU on it!". That is like an electronics novice thinking that they will be designing a superhet receiver and a 100W stereo amp and PSU as their first project. If you head down this road then odds are that the FPGA board will sit on the bench, and then languish the cupboard unused.

I strongly suggest that you think "I am a beginner student at the start of a long journey to learn how to design state of the art digital electronics. I need something on which I can play with and practice on and develop my skills before I shoot for the moon". Think how long it took you to get familar with analogue electronics - it is going to take a few hundred hours. How much did you spend on that journey for parts and tools?

Here's a video from somebody who is starting out, and taking the low road and just purchased what is almost a bare FPGA board - http://t.co/EYY82JedM6 -  how much more productive would he be over the next few weeks if he had spend an extra $40 on the pre-built board with the LEDs, switches, connectors, ADCs and so on? (http://papilio.cc/index.php?n=Papilio.LogicStartMegaWing).

Rather than slugging it out for a few months with a naked breakout board, soldering leds and wires, wouldn't you rather spend time working with a Digilent Nexys3? (http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS3) It may seem like a lot, but some people pay more than that for a multimeter...

If you can't spend more than $100, just get something like a Papilio One 250k and a LogicStart (~$75 for both). That is less than a good soldering iron - but will give you equivilent to a quarter of a million gates to play with, and you won't need that soldering iron. If you out-grow it can then dedicate the Papilio one to a project, and get a Papilio Pro as your new development board.

But in general the *second* board you buy will be the breakout board you use in your first projects - your first FPGA board is what you will design that project on.

[mikeselectricstuff]

Lattice XO2 devices mop up a lot of this messy stuff - internal core voltage regulator, flash and even an oscillator, albeit with only 5% accuracy.

..and does anyone use platform flash these days now that SPI flash is so cheap?
You can in most cases program it through the FPGA, avoiding the need to have seperate connections to the programmer.

I really don't understand why FPGAs don't include at least an MCU style osc that you can connect a crystal to.

Would you recommend one of those XO2 breakout boards as a cheap way to get into FPGAs?

I don't really fancy forking out £100+ on an FPGA board because I probably won't use it enough!

I do like the fact the breakout board gives you access to virtually every pin so you are not bound to use peripherals that are pre built on the board.

Yes, definitely
http://uk.mouser.com/ProductDetail/Lattice/LCMXO2-7000HE-B-EVN/?qs=sGAEpiMZZMurtJ7VwBTl0fuXvMOPgNe8hSHI90CFJ0k%3d

Thanks Mike

£17 is a really good price. Shame the delivery is £12 though, know of any other places that may be cheaper?

Free shipping if you can get the order up to £50.

[Rigby]

I remember discussing with a friend a while ago; wondering when someone was going to make the "Arduino of FPGAs" that is easy to build with and program with. 

Probably never, as you will always have to use the vendors place & route tools. You could make a nice front-end that called these & package it all up, but even if done really well it would still have a significant compile time.
This is where CPLD may be better, but probably too limiting.

Yeah, that front end thing worked out well for altium

That doesn't make it a necessarily bad idea.

A well done front end and a little bit of end-user knowledge will go a long way.  From what I've seen of the Xilinx and Altera tools there is a great deal of improvement to be done.

It would be nice if there was some UI paradigm that grew the UI complexity as your understanding of the tools grew.  Something beyond the "basic" vs. "advanced" setting commonly seen.

[Zad]

I think the problem with software is exactly the same problem that Altium had - trying to be all things to everyone. The user interfaces all seem to look like something from the OS/2 era. I remember in the early 90s when I first got Borland C++ developer for windows, and it had an editor which allowed you to put as many icons, sub-windows and scrolly widgets as you wanted onto a nice "big" 800x600 window. They don't seem to have progressed much beyond this point.

I would say that it is a lack of competition which has stifled development of the UI, but CAD offerings as diverse as Eagle, LTSpice, Kicad etc all seem to suffer from the same failings.

[Russ.Dill@gmail.com]

Yes, with a microcontroller, you never ever have to think even a moment about configuration memory. Its awesome, but I think that Dave makes the situation with FPGAs more intimidating than it needs to be.

A simple SPI flash is all you need. Its very low pin count and doesn't need a connection to the JTAG chain. The SPI flash can be programmed indirectly by the FPGA through JTAG, which is supported by the tools. The number of pages dedicated to supporting external SPI flash and indirect programming is pretty small. But again, as he warns "young players", there are many things you can get wrong and if you do, it can be absolutely maddening to debug.

And as another poster has pointed out, the configuration clock is available after configuration, but the frequency is not very precise.

(/me rolfs at the "Dave Jones" edition in the demo video)

[AlfBaz]

That doesn't make it a necessarily bad idea.

A well done front end and a little bit of end-user knowledge will go a long way.  From what I've seen of the Xilinx and Altera tools there is a great deal of improvement to be done.

It would be nice if there was some UI paradigm that grew the UI complexity as your understanding of the tools grew.  Something beyond the "basic" vs. "advanced" setting commonly seen.

I have to admit that I got into fpga's using altium's front end. It really was a blessing as it initially hid some of the more esoteric nuances of programming fpga's

As the level of complexity in my construct's grew I found I was resorting to the underlying synthesizer more and more until I eventually did everything in ISE

[nixfu]

As a "micro-guy".  I just have not yet gotten what you do with an FPGA. 

I dont mean applications like DSP, ADA, etc.  but as a dev, what are you doing?   do you break what you want to do down into individual logic gates?   or do you mostly end up putting together/using pre-built special purpose cores?

i am an experienced developer with many platforms and languages but the FPGA seems even removed from using an assembler, yet I just cant wrap my head around the concept.

[hamster_nz]

As a "micro-guy".  I just have not yet gotten what you do with an FPGA. 

I dont mean applications like DSP, ADA, etc.  but as a dev, what are you doing?   do you break what you want to do down into individual logic gates?   or do you mostly end up putting together/using pre-built special purpose cores?

i am an experienced developer with many platforms and languages but the FPGA seems even removed from using an assembler, yet I just cant wrap my head around the concept.

Yes, all of the above.

You can do 'structural' designs where you wire pre-defined components together - much like a building a system's schematic. This is what I think most people with an electronics engineers background think that FPGAs are for - replacing lots of little chips.

You can do data-flow designs, where you set up a data stream that enters the FPGA, does stuff, and then exits the FPGA. (e.g. audio processing) - very much like a hardware based UNIX "filter" program. This is very DSP friendly - and this is what most computer S/W people think FPGAs are for.

You can do sequencing style designs (called Finite State Machines or FSM in the local jargon), where you build a state machine that does something special. This is what most embedded engineers think FPGAs are for -  bitbashing high speed I/O and adding custom MCU peripherals and so on.

You can also be designing a very advanced state machine, which looks much like a CPU. This is what Computer Scientists think FPGAs are for - playing with computer architectures.

High-end H/W suppliers think of FPGAs as a low cost / rapid development replacement for ASICs, when volume and/or performance requirements are relatively low.

And then ASIC developers think FPGAs are a way to validate the logic behind their designs before they get put into real silicon.

You usually end up doing a whole lot of things at once (except of course the last two!).

So maybe a CMOS camera system has a small CPU that controls the camera's I2C interface a data stream to receive the pixels from the camera and process them. They can then be put into a frame memory using a pre-designed memory controller block. After that it could then be displayed using a video controller, which is just PWM system which seqences accessing memory and squirts the pixels out to the DAC.

Some bits you will build at the gate level, other bits you build at the block level. Usually the closer you are to the input pins on the FPGA the closer to gate level you need to work, or perhaps you are trying to make the most of an internal DSP block where using tricky features can make huge performance gains.

Much like using software libraries, doing things with high-value pre-defined blocks usually costs real money, as you need to license them from the original developers.

[EEVblog]

I think FPGA's are a bridge too far for hobbieists, they usually are extremely large and expensive and used for prototyping large circuits such as video circuits and such.
Nice for companies and pro's but not for amateurs.

The problem is that there are relatively few applications that can't be done (even if inelegantly) with a microcontroller these days.
So learning a entirely new way to conceptualise problems and "code" them is a very steep curve. Let alone the complex tools and setup required to get them working properly as well.
So it's a huge step to get into what is ultimately a niche application area.
Almost everyone remotely technical is familiar with traditional sequential processor based programing, so something like the Arduino or other micro solution is a snap to understand and pickup and use. But FPGA's aren't even close to that I'm afraid.

[EEVblog]

Do NOT compare FPGA and microcontrollers. They are totally different beasts. Yes, you can plonk a softcore in the larger ones but those are only used to do stuff that is too complex to synthesize into hard logic. Apart from some very niche applications no sane system designers cams the entire logic + cpu in an FPGA. they are too expensive for that.

And that is why Altium betting the entire company that this would be the future of electronics failed so miserably 

[darrell]

On Xilinx parts, the configuration clock is available after configuration. I have used it to get the real clock initialized.

Which one(s)?  CCLK is supposed to go tristate shortly after configuration from an FPGA in master mode.  For slave mode, I am not sure what CCLK from a Xilinx configuration PROM does, but I think that stops too.

Spartan 3E, 3A, 6 and 7 Series, at least. The pin does go tristate, but there is a primitive called STARTUPE2 (Kintex 7, may be some other variation on STARTUP for others) that provided the internal CCLK oscillator as an output.

[miguelvp]

The funny thing is that the world is concurrent and everything we do is also concurrent. We are taught being sequential because it does have advantages but with the prevalence of multicore computing we are going to need to shift to more functional programming paradigms. Note that a lot of new functional languages are being developed and on the last 10 years old functional programming languages have gained a boost (like Haskell and Erlang)..

Here is a two part interview with Joe Armstrong (father of Erlang) 30 minutes each on his thoughts about concurrency.
http://channel9.msdn.com/blogs/charles/jaoo-2007-joe-armstrong-on-erlang-oo-concurrency-shared-state-and-the-future-part-1
Edit: this 2nd part goes more into FPGAs.
http://channel9.msdn.com/blogs/charles/jaoo-2007-joe-armstrong-on-erlang-oo-concurrency-shared-state-and-the-future-part-2

Btw an ATM exchange made by Ericsson running Erlang (the AXD301) supposedly achieved a reliability of nine nines (31.5 milliseconds/year downtime)

In these interviews he touches on the concept of Erlang running on FPGAs and some already to this.

Like this group uses them for correlating data from several remote radio telescopes with different packet formats to work as one in real time. One board with 8 FPGAs can process 16 Gbits/second in real time, and they claim the code was so easy to write that they were able to convince management to green light them.


Maybe there is not going to be a programming paradigm shift but I rather be ready so I can hit the ground running.

[Kjelt]

As a "micro-guy".  I just have not yet gotten what you do with an FPGA. 

Let me give it a try from another perspective a bit black/white but just to make it clear (for the example I do not include softcores in FPGAs because then you have another hybrid and the discussion would be less clear):

A microcontroller is a circuit that was designed to be flexible, dynamic, to be able to do almost anything depending on how you program it and able to change quickly with different programs, user scripts as you like. It was designed to be re-configured (running its code) on the fly.
The counterside to this ultraflexibility is that it is pretty slow, think of cycles in us (microseconds).

A FPGA is a fixed circuit that after being programmed performs (a multiple of) a single core functions, less flexibility but is able to do this task ultrafast, think of throughput of 5 to 10 ns (nanoseconds).

So to give you an example when you need a FPGA and can not use a microcontroller:
- continuously extract and output the audio stream from an incoming digital HDMI stream of 5Gbps.

[hamster_nz]

Which one(s)?  CCLK is supposed to go tristate shortly after configuration from an FPGA in master mode.  For slave mode, I am not sure what CCLK from a Xilinx configuration PROM does, but I think that stops too.

Spartan 3E, 3A, 6 and 7 Series, at least. The pin does go tristate, but there is a primitive called STARTUPE2 (Kintex 7, may be some other variation on STARTUP for others) that provided the internal CCLK oscillator as an output.

Well, I just had to try it:

Code: [Select]

STARTUP_SPARTAN6_inst : STARTUP_SPARTAN6
   port map (
      CFGCLK    => open,       -- 1-bit output: Configuration logic main clock output.
      CFGMCLK   => test_signal,
      EOS       => open,         -- 1-bit output: Active high output signal indicates the End Of Configuration.
      CLK       => '0',          -- 1-bit input: User startup-clock input
      GSR       => '0',          -- 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
      GTS       => '0',          -- 1-bit input: Global 3-state input (GTS cannot be used for the port name)
      KEYCLEARB => '0'           -- 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
   );

I routed test signal into my frequency counter project's input (rather than using an external pin) and this is what I got:

Code: [Select]

...
053,153,413
053,154,512
053,155,198
053,152,184
053,152,781
053,150,509
053,150,583
053,151,034
053,151,486
053,148,068
053,148,444
053,146,664
053,145,952
053,146,836
053,143,573
053,142,675
053,145,679
...

The frequency looks to be temperature sensitive - the dip in the attached graph is when I warmed the FPGA with my thumb. It is about 5 minutes worth of samples

[free_electron]

Here is how i use FPGA's :

I have a machine that can play a digital pattern. This machine is stupid. It can only play the pattern from a begin point , to an end point and then go to an intermediate point and keep looping.
Lets say ot starts at line one, runs to line 1000 and then goes to line 500. It now endlessly runs from 500 to 1000 after which it jumps to 500 and so on.

I want to give this thing more intelligence. The machine itself cannot be altered. It is huge (a whole room full of 19 inch racks).
So i do the following : i create a 'compiler' for a software language that can create flat paaterns (loops etc need to be unrolled). I use one of the pattern bits as a clock bit, the rest is used as command/data.

I feed the pattern to an fpga. In there i create a bunch of logic that can decode these commands and take action. One such command is : test current and see of it is in side two boundaries.
The boundaries were set once in the non-looping part. When the command is requested a bunch of a/d comverters need to be read and checked against a min and max value.
These a/d converters hang off SPI buses.

Commands arrive at a rate of 1MHz. There are 32 ad converters that need sampling and comparison.

Let's try this with a cpu shall we ? First of all SPI has a limited bandwidth. The A/D converters can't be clocked much faster than 30MHz ... The SPI frame is 14 bit , looking at the pattern we need one clocktick to make cs low, then 14 clockticks to get the data and another tick to make cs high. 16 clockticks. So, if i want to be able to get the data from 1 convertor i need to be able to do this in 1/16 of a microsecond (remember new commands arrive every 1 microsecond without stopping ! So i need to be able to do this, guaranteed, in the given timeframe)

Using a cpu clocked at a hundred MHz i could do this no problem. For one channel. But there are 32 that need doing ... Even 4 or 8 channels become problematic for a cpu ...
So i created the spi interface in the fpga. The fpga spits out a cs and a clock to the a/d convertors. The data lines of the A/D are being fed back in parallel. So 32 serial streams are entering, each on a pin of the fpga. I get 32 readings synchronized in time back. 32 shifters in the fpga trap this and 32 hi/lo comparators against 64 registers (each a/d channel can have different hi and lo setpoints.) test this captured data in 1/320 of a microsecond (my fpga master clock is 320MHz). If an out of bounds is detected i kick of an interrupt to an external cpu. The cpu has access to the captured data stored as a chunk of ram. The cpu is unaware that the comtents of this ram are altered by hardware. The whole operation happens much faster than the cpu can even execute one instruction.

In short FPGA's are used to solve time critical, parallel problems in hardware. Doing things where a cpu would fail because it doesn't have enough time to do it. You create hard logic.

Practical examples : HD video playback. Many of the early plasma and lcd tv's were based in altera fpga's. Before the mass market custom chips were available this was the only way to play 1920x1080 .. Cpu's were too slow and the asics werent there yet. So we shove it in an fpga.

Another examp,e : take a look at foto_opa website. He makes pictures of insects in flight.
He uses an fpga to control two crossbeam lasers, focuse detection, shitterspeed calculation , flash delay calibration etc.  his system is self configuring. It takes a trial shot, establishes flash and shutter delay , and it is ready. If an insect flies through the crossbeam the fpga know, within 1 microsecond, what to fire and when to fire. A task impossible, even on the fastest cpu simply because the i/o is too slow and there are too many things to do that are time critical. A cpu needs to do a whole sequence of instructions , an fpga does it all in 1 clockcycle.

[curiousbob]

For those knowledgeable in FPGA design:

When looking at a particular module/entity or even a larger design consisting of multiple modules/entities are you able to look at the rtl and quickly understand how it works and what is happening or do you find it necessary
to spend time dissecting it and perhaps simulating it in order to understand it and possibly customize it for your own needs?

[miguelvp]

For those knowledgeable in FPGA design:

When looking at a particular module/entity or even a larger design consisting of multiple modules/entities are you able to look at the rtl and quickly understand how it works and what is happening or do you find it necessary
to spend time dissecting it and perhaps simulating it in order to understand it and possibly customize it for your own needs?

Will be the same as in C or C++, how many times do you resort to look at the generated assembly language and do you understand the assembly language generated without looking at the C function or C++ method?

With the added understanding on how an assembly op code actually works and what register flags are touched.

As far as the HDL code same thing, it all depends how it's written a monolithic module with nonsense variable names, poorly structured and undocumented will be as hard to understand as their counterparts in C or C++.

I only been using FPGAs for 6 months an change on my spare time so I have to lookup things every now and then because they have not become second nature just yet. But I have no problem understanding what a piece of VHDL or Verilog that others wrote. Even large projects since most tend to be very modular.

[hikariuk]

For those knowledgeable in FPGA design:

When looking at a particular module/entity or even a larger design consisting of multiple modules/entities are you able to look at the rtl and quickly understand how it works and what is happening or do you find it necessary
to spend time dissecting it and perhaps simulating it in order to understand it and possibly customize it for your own needs?

Will be the same as in C or C++, how many times do you resort to look at the generated assembly language and do you understand the assembly language generated without looking at the C function or C++ method?

About the only time you look at assembly nowadays, ime, is when you need to get really greasy in a debugging session.  Or you really want to tweak the output of the compiler.

I suspect the vast majority of developers never look at assembly anymore.

[miguelvp]

Will be the same as in C or C++, how many times do you resort to look at the generated assembly language and do you understand the assembly language generated without looking at the C function or C++ method?

About the only time you look at assembly nowadays, ime, is when you need to get really greasy in a debugging session.  Or you really want to tweak the output of the compiler.

I suspect the vast majority of developers never look at assembly anymore.

And that was my point, no one needs to work at the RTL level.

[curiousbob]

Writing code at the RTL (Register Transfer Level) level using an HDL langauge is the most common way to design... at least that's the impression I have.

With C/C++ you have a sequential order of execution and can follow a program as it executes in a certain order.

With FGPAs there is no "order" of execution. Everything runs in parallel. The order of written code has no bearing on order of execution.
This to me is what makes undertanding a module/entity more difficult than a C function. When a module/entity comes with written documentation, it is a lot easier to understand whereas a C/C++ function can be more easily understood with the embedded comments.

[miguelvp]

Writing code at the RTL (Register Transfer Level) level using an HDL langauge is the most common way to design... at least that's the impression I have.

HDL and RTL are as different as C/C++ and the machine language it generates, check out the following thread as an example.
https://www.eevblog.com/forum/microcontrollers/(verilog)-using-non-blocking-assignments-reduces-le's-by-half!/

With C/C++ you have a sequential order of execution and can follow a program as it executes in a certain order.

With FGPAs there is no "order" of execution. Everything runs in parallel. The order of written code has no bearing on order of execution.
This to me is what makes undertanding a module/entity more difficult than a C function. When a module/entity comes with written documentation, it is a lot easier to understand whereas a C/C++ function can be more easily understood with the embedded comments.

Of course there is an order, all instructions execute at once but you can program it to do sequential things as well in any event you look at the events and do all the assignments needed, not hard to follow in Verilog/VHDL. Also you can embed comments in Verilog/VHDL so that others understand what you are doing.

[mikeselectricstuff]

Writing code at the RTL (Register Transfer Level) level using an HDL langauge is the most common way to design... at least that's the impression I have.

The HDL produces RTL but you rarely look at it.

This to me is what makes undertanding a module/entity more difficult than a C function. When a module/entity comes with written documentation, it is a lot easier to understand whereas a C/C++ function can be more easily understood with the embedded comments.

huh? A module can have comments (though one of VHDL's retardednesses is it has no block comments)

[curiousbob]

Wow! I'm not sure where to start...

An HDL language such as Verilog or VHDL allows one to design at the behavioral, RTL, or gate level.
Far and away the most common is at the RTL level.

http://hdlprogramming.blogspot.com/2010/01/levels-of-abstraction.html

[miguelvp]

Wow! I'm not sure where to start...

An HDL language such as Verilog or VHDL allows one to design at the behavioral, RTL, or gate level.
Far and away the most common is at the RTL level.

http://hdlprogramming.blogspot.com/2010/01/levels-of-abstraction.html

From your link:

We use VHDL, Verilog, System Verilog and even Schematics that defines the Behavior. The toolchain then converts that to RTL that is machine independent, but I never seen anyone working on this directly (RTL):
 

[hamster_nz]

We use VHDL, Verilog, System Verilog and even Schematics that defines the Behavior. The toolchain then converts that to RTL that is machine independent, but I never seen anyone working on this directly (RTL):
 

I have. When designing high speed output structures I've been working at RTL level, which in the context of FPGAs is a structural definition of which primitives are used an how they are connected. I had to to get 1.5Gb/s out of a Spartan 6 which is only rated for 1.0gB/s -allowing me to do 1080p - see http://hamsterworks.co.nz/mediawiki/index.php/Spartan_6_1080p

IMO the difference between RTL and behavioral structural is very fluid anyway. You can mix all three styles in the the same bit of HDL if you like. You can have a RTL description of the system interfaces (e.g. DDR, input & output buffers and clocking), behavioral description of the logic, and structural description of how sub-components are connected.

[curiousbob]

From wikipedia:

Register-transfer-level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Design at the RTL level is typical practice in modern digital design.[1]


Here is an example of a multiplexer at the gate-level (in verilog)
    mux u3 (mux_out, din_1, din_0);

And at the RTL level
    assign mux_out = (sel) ? din_1 : din_0;

An 8-bit shift register at RTL level?
    reg  [7:0] sreg;
    always @(posedge clk)
       sreg <= {sreg[7:1], datain};

[miguelvp]

Good to know there is access to it, kind like an asm block in C/C++, still you can put comments

I guess I have to learn RTL and what gate level modules are available in VHDL, but not ready for that level of control just yet.

[FrankBuss]

I think behavioral structural can use anything the language provides, like "wait for 100 ns" in VHDL, which no tool I know can synthesize to a FPGA. As you can see in the diagram from miguelvp, RTL is still FPGA independant. The tools are really good, e.g. they can infer and synthesize block RAM from standard VHDL or Verilog code, without using the special architecture dependent primitive. But in a RTL description you can also use primitives of the target FPGA and do a very low level netlist description style, too, but nobody would do this, except for special cases as hamster_nz wrote. For very high speed designs you might even need to specifiy the layout, to place components on the FPGA where you want it. I know someone who did this with a Cyclone FPGA and LogicLock for a 3G SDI codec.

[curiousbob]

Just about nobody designs at the behavioral level as it is not synthesizable. Behavioral level coding is mainly for simulation/verification (i.e RAM and bus models)

I get the distinct impression that some call RTL level description behavioral description for whatever reason.
RTL is usually used to describe synthesizable code.

[hamster_nz]

I get the distinct impression that some call RTL level description behavioral description for whatever reason.
RTL is usually used to describe synthesizable code.

• Structural is how the sub-components are connected, without any discription of how things work (e.g. no details of logic or registers, just blocks and wires)
• Behavioral is how I would like this to module to work, allowing the toolset to handle the implementation details
• Register-transfer level is how the module will work, with a clear seperation of logic and registers

Synthesizable or non-synthesizable is somewhat fluid too depending on your target platform. For example RTL code that has a register that is senstive to both edges of a clock it will not synthesizable on most platforms.

And the difference between RTL and Behavioral is somewhat blury. Take for exmple this code:

Code: [Select]

  this_term  <= value * c;
  next_sigma <= sigma + this_term when reset = '0' else this_term;

  process(clk)
    begin
      if rising_edge(clk) then
        sigma <= next_sigma;
      end if;
   end process

It is describing the logic (how this_term and next_sigma are calcuated) and the registers (in the clocked process). So this looks clearly like RTL.

Oh, except for the multiply operator. Maybe the whole thing get merged into a MAC function on a DSP block? If it can, how can this code be RTL, surely it must be behavioral?

[curiousbob]

Behavioral and RTL are not my terms. Neither are their definitions. However, behavioral
is one level of abstraction higher than RTL.

The term RTL can be a little confusing. The code for a multiplexer, for example, is considered RTL
yet, by itself, has nothing to do with registers.

As you say, the line between behavioral and RTL can be blurry. In some instances the main distinction between the two
is that one is synthesizable while the other is not.

Now, the multiply operation could be implemented entirely in FPGA fabric using shifters and adders but is is much
more efficient and faster if implemented in a DSP slice (which the synthesis tools will likely do). The fact that, hardware-wise,
you've told the tools how this_term is to be implemented (multiplication of value and c) is what
determines this as RTL rather than behavioral. Behavioral usually gives no information at all how something is implemented
and, as such, is not synthesizable.

http://www.ohio.edu/people/starzykj/network/class/ee690/slides/behrtlpresent.pdf

[vlad777]

Just use CPLD in PLCC44 package:
Lattice iM4A5-64/32 (EEPROM)  or XILINX XC9536 (Flash)

This is my attempt on CPLD-s :  http://electro.freeserverhost.com/xilinx_programmer/xilinx_programmer.htm
I am doing something very similar with Lattice chip right now.