Errata:
@13:40 ish: the scales are log-log in that type of curve, so, it doesn't go to DC and infinity.
@18:10 ish he kicks; 18:45 misses the field goal.
The 'sum' curve
necessarily must rise above the constituent curves, where they intersect. This is a real effect (central to the thesis), and cannot be ignored, whether invoking complex numbers or not!
@ anywhere: although trace inductance is mentioned (so this point is fair game!), the inductance between caps, and from caps to the device pin, is not mentioned.
Here's an example of the correct sum:
I'm using pulled-out-of-my-ass numbers here, but they're approximately representative. The ESL is approximately proportional to geometry scale, typical for 1206, 0805 and 0603 or the like. The ESR is a typical guess; do look up the real values if you're going to do this. (Somewhat more accurate SPICE models are given by the usual database programs -- TDK SEAT and Kemet SPICE, and I think others have similar; but beware these produce fixed-frequency models, so you need to pick a representative frequency as a starting point. YMMV.)
The impedance plot is:
As you can see, the two peaks are prominent, over 0.3 ohm: greater than even the ESR of the smallest cap, and worse than a single ESL of 8.5nH. Even though, naively looking at the topology, there should be somewhat less than 4nH because of parallel combination.
But in the real world, we cannot place capacitors in precisely the same place! There must be inductance between them as well. Trace lengths, as well as component body lengths and via lengths, count against both the capacitors' ESL, and introduce inductances between them.
(Vias aren't relevant in the demonstrated example, with parallel strips on the same layer -- but they are relevant to most PCBs, where SMT pins are routed and bypassed on an outer layer, and ground is on an inner or opposite layer.)
This looks like:
Note I rearranged the source, and added another capacitor on the left side. The larger inductance represents a couple inches of trace length, and the higher ESR and C represent a bulk capacitor, like the bypass on a linear regulator for instance. The voltage source is serving as a probe, where the device pin would be, so we measure the impedance into that location only. (The plot computes V(V1) / I(V1), the impedance seen by V1.)
Note also that ground is assumed ideal,
which isn't the case, but a ground plane is close enough to ideal so I won't bother taking the time. Anyway, accounting for that (or, if your board is actually routed that way, as Ye Logic Boardes Of Olde, with VCC+GND routed beneath the rows of ICs), just adds more series inductance between parts, so it's not topologically important. (It does, however, introduce common mode inductance, which means you get ground bounce between ICs. All kinds of messy!)
The impedance plot,
is much higher (notice the scale change!), peaking around 2 ohms before running away again in the high frequency limit.
Notice how it's flattening out at low frequencies. It plateaus to, you guessed it: about 1 ohm there. (At still lower frequencies, it rises again, but only because there's no regulator. A real regulator would show decreasing impedance to the left, giving good regulation near DC.)
That it plateaus to something stable, is both interesting and useful!
So, what can we do about the high impedances?
One cannot escape the fact that, the power supply rail is a Power Distribution Network (PDN). As with any network, it can be approximated as an RLC equivalent. The basic RLC parts are the ESR, ESL and C from the capacitors, and series L from trace lengths and vias (and sometimes capacitance as well). (Dave kind-of mentioned trace capacitance: however, there is a much more interesting reason beneath that!)
When looking at a network, we must observe two things: impedance Z and frequency F. The frequency response of a network depends on only these parameters, and how the impedance and frequency of a given stage (i.e., a single LC unit in the chain) vary from the mean value within the network. If we want to optimize for a particular goal (such as low impedance over a wide frequency range), we have to learn to work within this domain!
How do Z and F correspond to the circuit? Very simply:
\( Z_0 = \sqrt{\frac{L}{C} \)
\( F_0 = \frac{1}{2 \pi \sqrt{L C}} \)
Any time you have a chain of series L and parallel C (series meaning, spanning horizontally from branch to branch; parallel meaning, vertically from branch to GND), you have something that looks suspiciously like a transmission line.
Traces are fundamentally transmission lines. At low frequencies, we approximate TLs as a single inductor or capacitor: which one we choose depends on how the circuit impedance compares to the TL's characteristic impedance. Lower and it looks inductive, higher and it looks capacitive.
The frequency is "low" when it's below, say, 1/10th the electrical length of the TL. At 100MHz, this is 30cm. A 100 ohm trace, 30cm long, has about 115nH of equivalent inductance, and will measure this value over quite a wide range (about 3 decades: from ~100MHz down to ~100kHz, when DCR (~0.1 ohm?) takes over).
PDNs are intentionally very low impedances, so we'll only be concerned with traces as inductors. For other circuits, like sensitive analog, or RF, signal impedances can be quite high (kohms, Mohms even!), and we would be concerned about equivalent capacitance instead. (All the same reasoning used here still applies, but you're getting caps instead of chokes!)
PDNs also do their work in the "low" frequency range. Trace lengths between capacitors and devices are millimeters, while the frequencies of interest top out at 100MHz or so. (It's not practical to try to design a PDN beyond 100MHz, and most ICs do not require the PCB to be that good. Manufacturers have to deal with this range themselves, which is why very large CPUs have onboard capacitors. Furthermore, within the die itself, vast swaths of parallel metal layers provide very "fast" capacitance, to respond to the tens-of-picoseconds switching edges the transistors produce!)
So we can approximate traces as inductors. Whoop de do. Where's the magic?
The magic savior is resistance! Use ESR to your advantage. Any time you have loss (equivalent resistance) comparable to reactance, you have a well damped resonant circuit, and instead of peaks and valleys, you get humps and dips.
You can solve for the ideal circuit, by calculating backwards from the pin itself.
1. Suppose the pin is 5nH (a couple mm length from die to PCB pad). It's a VCC pin, adjacent to a GND pin, on, say, a TQFP packaged microcontroller. (There are probably four or more pairs of VCC/GND pins around the chip -- simply solve for one, and repeat the layout for all of them.)
2. The microcontroller demands peak currents up to 100mA (per pin pair / IO bank), regulation better than 10% (i.e., no peaks or dips or ringing beyond +/-10%), and has a 3.3V supply. That means delta V <= 0.33V, and Z <= 3.3 ohms. This is required up to 50MHz.
3. The pin itself has 5nH, which has a reactance of 3.3 ohms at \$ F_{\textrm{max}} = \frac{3.3 \Omega}{2 \pi 5\,\textrm{nH}} \$ or 105MHz, so we only have about 50% overhead for ESL to the first cap.
4. We'll use an 0603 0.1uF cap near the pin pads: this will be around 3nH. Total inductance to the device is now 8nH, so we expect to achieve 2.5 ohms at 50MHz. At that frequency, the capacitor looks inductive (Xc = 0.032 ohms, less than the ESR even, so ESL is dominant), and the voltage dropped across the ESL is a modest fraction of the voltage at the pin (the pin ESL and cap ESL act as a voltage divider).
5. We can resonate the ESL with another capacitor. Now here's the magic: if we can choose components so that the impedance \$Z_0 \leq \textrm{ESR}\$, we can have the ESR dominate, and the resonance will be damped! We're starting with about an ohm's worth of ESL, so we have to add an ohm of ESR somewhere.
6. We could put a resistor in series with the cap, or we can put an R+C in parallel with it. A series resistor will itself have ESL, making things too much worse, so let's do the latter. R = 1 ohm and \$C \geq 2.5 \times \$ the other cap (i.e., 0.25uF -- 0.33uF or 0.47uF is the next closest value).
This looks like:
I've assumed an 0603 is reasonable for 0.47uF, which certainly is true for a 3.3V supply (I'd recommend a >= 10V X7R part, readily available).
Note how flat it is (relatively speaking), and there are no peaks! Indeed, it flattens out to 0.5 ohms in the middle there, where the supply acts in parallel with the local "bulk" cap -- which itself isn't really very bulky, and could be smaller while still serving the same function.
We don't even really need the 0.47uF at all -- in the <10MHz range, the supply itself is doing a fine job. With the 0.47uF removed, the curve stays flat at 0dB (i.e., 1 ohm) until the notch.
The notch, by the way, is 3nH + 5nH and 0.1uF ==> 5.8MHz. Eagle eyed readers will have spotted this.
8. What if we want to do better?
We can't really raise the high frequency limit, because that's the manufacturer's problem, due to pin geometry. (With some series-resonant trickery, it can be pushed closer, but I won't go into that here.)
If we wanted to make the 'mid-band' lower and wider, we can simply add larger capacitors in parallel. Because the frequencies are low, they can be placed at modest distances (10-30nH), which makes them very easy to place. But we can't go crazy, either: a few electrolytic or tantalum will improve things, because their ESRs will act in parallel, presenting a reasonable resistance (say 0.1-0.5 ohms) across a wide spectrum, without making things resonate. But ceramics or aluminum polymers, untamed by added ESR, will make things significantly worse...
This is just removing the ESR from the 0.47uF, and shoving it a few cms away, so it's about midway between the supply and the pin. How horrible!
However, it's noteworthy that we still haven't blown the spec. The supply will ring noticeably at the peak there (3nH + 3nH + 15nH and 0.47uF + 0.1uF ==> 3.8MHz), but with an impedance of 1.7 ohms, it won't ring worse than about 2.5% of the supply (~85mVpk), and that's if the MCU thrashes multiple simultaneous GPIOs at the resonant frequency!
This is the reason why manufacturers and appnotes almost always suggest capacitor overkill: if you don't know any better, adding more caps is
probably not going to make things critically worse. But it often won't make things any better, and a critical analysis of the network, and its properties, will show why that is true.
Cheers,
Tim
Home
Help
Search
Login
Register
