EEVblog #859 - Bypass Capacitor Tutorial

[EEVblog]

Everything you need to know about bypass capacitors.
How do they work?
Why use them at all?
Why put multiple ones in parallel?
What effect does package type have on performance?
Are there any traps?
Dave measures some bypass capacitors with an impedance analyser to confirm the whiteboard theory and shows the complexities involved.

Reverse geometry packages:
https://product.tdk.com/info/en/catalog/datasheets/mlcc_commercial_lwreverse_en.pdf
Low inductance chip capacitors:
http://media.digikey.com/pdf/Data%20Sheets/AVX%20PDFs/LICC.pdf

[dentaku]

Now there's a video Elecia White should be interested in watching. She's mentioned the mystery of bypass capacitors many times on embedded.fm.

[apis]

Nice to see reality as well as whiteboard.

[papo]

Hum did Dave goof up the formula for C_IMP? This doesn't look quite right...

[ROBOT]

So if I know the noise on my power supply is say 20kHz how would I go about choosing a bypass capacitor value?

[c4757p]

Hum did Dave goof up the formula for C_IMP? This doesn't look quite right...

Yes, he did. Summing the real reactances doesn't work, they have to be complex impedances... He also mixed up terms for impedance, reactance, and resistance all over the shop...

[EEVblog]

Yes, he did. Summing the real reactances doesn't work, they have to be complex impedances... He also mixed up terms for impedance, reactance, and resistance all over the shop...

I deliberately didn't want to get into the complexities of all the detail of that so I simplified it.
I think I even mentioned it was a gross simplification at some point.
Start introducing complex numbers into the explanation of this and you immediately start losing your audience.

[leafi]

I have a question, if all of these capacitors have the same ESL 1nf, 10nf, 100nf 0402 and all are the same dielectric would a better bypass arrangement occur from having one of each or use 3 100nf caps in parallel. Basically when I look at kemet spice or TDK seat the ESL and ESR of the caps are pretty much the same for different values for some of them. Personally I would think if they all have lets say 1nH of inductance each that the XL reactance curve should all go up on the right in the same line. (minus Q related artifacts).

[c4757p]

Dave, with all due respect - if you wanted to simplify it, then I don't think you should have given the equation at all. That equation isn't simplified, it's wrong. It doesn't work with real numbers. You could have explained the topic without giving people equations (which they are now going to remember and try to use at some point) that don't work.

[uncle_bob]

So if I know the noise on my power supply is say 20kHz how would I go about choosing a bypass capacitor value?

Hi

Without knowing a *lot* more than the frequency, picking a cap (or a bank of caps) is a bit premature.

1) Is the noise a sine wave tone or a square wave ripple? Different approach for each of those.
2) Is the noise broadband with a peak peak at 20 KHz? again a special case
3) Is the noise from the load rather than the supply? Again a different set of things to look at.
4) Is this some sort of massive supply current wise? (I have a 100A adjustable sitting over there .. some day I'm *sure* it will move it's self. I certainly am not picking it up ..).
5) Is this some sort of very high voltage supply? (another bunch of odd caps to pick between)

That's just the here and there questions. You will eventually get to:

1) What is the output impedance of the supply at 20 KHz?
2) How much noise do you have?
3) How much noise do you want?

If the supply has a 0.01 ohm output impedance and 100 whatever units of noise. You want 1 whatever unit of noise. Your cap needs to be 0.0001 ohms at 20 KHz. If you start with caps that have a 0.01 ohm ESR, you will need at least 100 of them in parallel. Since we have a hundred of them, they each will need to have a reactance of <0.01 ohms at 20 KHz. A thousand microfarads looks like a good bet.

Yes those are bogus numbers. No they don't apply directly to *your* supply. You need the numbers for your device. It does illustrate that tossing caps at the problem *can* have it's downside. Even if you go to 0.1 ohms Zo, you still have a hundred caps with a pretty low ESR.

Depending on your answers to all the goofy questions in the first part, your supply may not *have* a well defined output impedance or it's noise may come from a stability issue. Your giant cap bank *might* make things worse. 

Bob

[EEVblog]

Dave, with all due respect - if you wanted to simplify it, then I don't think you should have given the equation at all. That equation isn't simplified, it's wrong. It doesn't work with real numbers. You could have explained the topic without giving people equations (which they are now going to remember and try to use at some point) that don't work.

Yeah, fine, you won't get much argument from me. Maybe I shouldn't have, but meh.

[ornea]

I have always been curious as to why they did not put power pins close to each other to reduce the pcb trace length to the caps.
I guess a tradeoff between making it easier to run power rails and longer traces like I see on old arcade pcbs.

But still ...

[c4757p]

Power pins are distributed around the chip so they can deliver power to different areas of the internal circuit. Somewhat unavoidable. Many modern chips put the pins in nice power/ground pairs, which makes it much easier to place decoupling capacitors, and also reduces the effective inductance by way of mutual inductance between the two. That's about as good as you can get, I think.

As for the placement of power pins on things like 7400 series that you'd see on old arcade PCBs - I have no bloody clue. The arrangement of power and ground on pins N and N/2 that 7400 series use seems really silly to me, I'd think using pins 1 and N would be much nicer.

[EEVblog]

I have always been curious as to why they did not put power pins close to each other to reduce the pcb trace length to the caps.

That's quite common these days in modern chips, power pins are often side-by-side.
But it's all a trade-off with the requirements for the die.

[EEVblog]

As for the placement of power pins on things like 7400 series that you'd see on old arcade PCBs - I have no bloody clue. The arrangement of power and ground on pins N and N/2 that 7400 series use seems really silly to me, I'd think using pins 1 and N would be much nicer.

A lot of it might come from convention. And it was actually beneficial to have power pins on separate sides of the package back in the day's of designs all having hundreds of chips, you'd just run +/- routing strip down the centre of all the chips, with decoupling straddling that. Made double sided designs possible. You could also chose to have the power rails running across the top and bottom of your line of chips, it was a pretty flexible arrangement from a layout point of view.

[orolo]

It's very nice that you pointed out the problem of resonance between caps in the video: I was waiting for that from the beginning, and the experimental results were adequately horrific (as in 26:52, decouple with three caps and make it worse.) Since my beginnings as RF homebrew aficionado I've been reading about never decoupling with different cap values, unless you really know what you are doing, and instead parallel similar caps. I've even read about people demanding from manufacturers high ESR caps, or trying to spoil the resonances with series resistors. It's a very complex matter, and I think many people derive a false sense of security from these widely different decoupling caps.

[EEVblog]

I've even read about people demanding from manufacturers high ESR caps, or trying to spoil the resonances with series resistors.

I've seen series resistors added. You must be pretty desperate to have to do that.

[Brumby]

Dave, with all due respect - if you wanted to simplify it, then I don't think you should have given the equation at all. That equation isn't simplified, it's wrong. It doesn't work with real numbers. You could have explained the topic without giving people equations (which they are now going to remember and try to use at some point) that don't work.

Yeah, fine, you won't get much argument from me. Maybe I shouldn't have, but meh.

I must admit I did wince a little at the simplified math - but it does not take away from the principle being presented.  I rationalised the expressions as being representative of complex numbers and I had no problem with it.  Besides, Dave has the overlay that states this simplification and the reasoning for it and, quite rightly declares: "The point is there is a total impedance that includes ESR, Xc and ESL."

I do understand how there will be some who will be rather irritated by this, but clinically correct mathematics is not essential to the understanding of the fundamentals.

[AustinTxBob]

I really enjoyed that video and it fits in well with the AC class I am taking right now. 

So lets say I built a circuit.  How would I see that I needed bypass caps and how would I determine the sizes and how many. I guess look for the ringing you mentioned?  Then add caps until that was minimized?

[strangersound]

Excellent class, Dave! Love the fundamentals series videos. Will definitely be reading the follow up exchanges here as well. 

[ElektronikLabor]

At work I use Kemet Spice to calculate the bypass capacitors: ec.kemet.com/tools
They also got an web based version: ksim.kemet.com/

Drawback: This simulator only KEMET offers capacitors

[GK]

I used to have a databook for a modified-package version of the high-speed (pretty sure) 74AC family. The pin count for each package was increased by 2 for an additional pair of VCC and GND pins. The power pins were placed in the middle with the pins of each pair (VCC, GND) directly adjacent, so that a parallel-pair power buss could be run right through the middle of the package, facilitating better high-speed layout/more effective supply-rail bypassing  (ie a 14-pin DIP became a 16-pin DIP with pins 4 & 13 = VCC and pins 5 & 12 = GND).

I couldn't find anyone at the time that sold these in small quantities. This was around about 1998-2000, about the time part of Motorola morphed into ON-semiconductor. I think it might have been a Motorola databook and initiative. That's about all I remember, besides the fact that the databook exclusively used that horrible revised IEEE logic symbol standard that no one seems to have adopted. I will never draw an (N)AND gate as a square box with an ampersand logogram in the middle!

[tggzzz]

Power pins are distributed around the chip so they can deliver power to different areas of the internal circuit. Somewhat unavoidable. Many modern chips put the pins in nice power/ground pairs, which makes it much easier to place decoupling capacitors, and also reduces the effective inductance by way of mutual inductance between the two. That's about as good as you can get, I think.

As for the placement of power pins on things like 7400 series that you'd see on old arcade PCBs - I have no bloody clue. The arrangement of power and ground on pins N and N/2 that 7400 series use seems really silly to me, I'd think using pins 1 and N would be much nicer.

74, 74LS, 74F series had well-controlled, relatively slow edge rates so that the inductance in the corner wires wasn't a major problem. Other 74 series with faster edge rates were more problematic, especially bus buffers w.r.t. ground bounce.

Eventually packages got smaller, the problems got worse, and backward compatibility became untenable/unnecessary, and power pins moved somewhere sensible.

[HAL-42b]

Can't we do something like a distributed capacitor? Supposedly a distributed capacitor may result in wideband operation.

[bktemp]

Can't we do something like a distributed capacitor? Supposedly a distributed capacitor may result in wideband operation.

That's the pupose of a ground+power plane on a multilayer board. A large power plane has a low inductivity and acts as a small capacitor. That simplifies decoupling capacitor requirements a little bit.

Decoupling capacitors are an interesting topic. For examples FPGAs. I have read application notes about decoupling, but it is impossible to do on cheap 2 or 4 layer boards without burried vias and other expensive stuff you can't afford unless you make thousands of boards because you need the top layer for routing all the signals.
I have compared many FPGA board from all kind of equipment (medical image processing, communication equipment) and the decoupling on all boards was much worse than the requirements from the FPGA manufacturer's application notes. One example is a board with a Virtex II FPGA and 8 DDR RAMs that has almost no decoupling capacitors except some larger ones. They are probably relying on the power planes for all the high frequency decoupling and only have some larger capacitors for bulk decoupling.