Author Topic: EEVblog #960 - Mystery Merry Mailbag Teardown  (Read 10839 times)

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Offline Carl_Smith

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Re: EEVblog #960 - Mystery Merry Mailbag Teardown
« Reply #25 on: December 27, 2016, 11:22:17 am »
So I dug out that box of old parts from some IBM equipment.  After all these years I don't remember what it was that these boards came out of.  But they show the same style of construction as the piece of test equipment Dave tore down.   Metal can modules, DIP ICs, and discrete components in a board with a grid of square vias with fine traces routed between the rows of vias.

Traces look autorouted, as nobody would do these types of paths by hand.  It seems there were rules like no T connections on traces.  Three way trace connections are always done with one of the square pad vias and the traces all connect to separate sides of the via.  Traces are also routed close to pads even when not necessary, as an autorouter would do to save space for future routes. 

The boards I have appear to be multi-layer.  If you put one over a light you can see light around each of the grid vias.  They also appear to possibly be coated on the outer layer with something that contains tiny air bubbles.   But none of the grid vias are coated - you can see the coating dip down and end around each of the square vias.

I will attach pics of a couple boards.  One large one with connectors in plastic bars down the sides, and a smaller one.  Also a shot of the large board lit from below so you can see the gaps in the internal layer around the grid vias, and a couple shots through the microscope of some of the strange trace routing.

I might have to do a YouTube video on these boards.

 
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Offline Carl_Smith

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Re: EEVblog #960 - Mystery Merry Mailbag Teardown
« Reply #26 on: December 27, 2016, 11:24:20 am »
And here is the smaller board and a couple microscope shots of the trace routing.
 
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Offline Cerebus

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Re: EEVblog #960 - Mystery Merry Mailbag Teardown
« Reply #27 on: December 27, 2016, 01:50:26 pm »
They also appear to possibly be coated on the outer layer with something that contains tiny air bubbles.

That coating is the solder mask. What you're seeing as bubbles in that layer are, I think, the junctions of the warp and weft of the underlying fibreglass rovings inside the board.
Anybody got a syringe I can use to squeeze the magic smoke back into this?
 

Offline alien_douglas

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Re: EEVblog #960 - Mystery Merry Mailbag Teardown
« Reply #28 on: December 27, 2016, 03:14:08 pm »
Don has a better memory than me.
Of course it was called the MD (Maintenance Device)

Dave, Dave, my memory is going.

The reason that you won't find tons of bypass capacitors is that these things worked at a snails pace compared to modern equipment. And they seemed to be very well designed, even if you don't like the grid PCB arrangement.

All the DIP chips will be IBM part numbered 74 or 74LS series 'Jelly Bean' chips. It was very rare to see a standard part numbered chip back in the day. Even the likes of 741 Op-Amps would be IBM part numbered. Engineers also had IBM part numbered Fluke multimeters, Tektronics scopes, Snap On tools etc etc.
There was a very specialised inventory control system, that Don will remember, called CEPICOS (Customer Engineering Parts Inventory Control On-line System.) that managed stock of millions of parts for IBM locations worldwide.

And as noted, all the grid holes in the boards are filled with solder. I imagine that the components were installed in the correct places and the board wave soldered, thus filling up all the unused holes.
They would have had another machine to solder on the spring contacts for the end connectors. Having had to replace munted contacts manually, it is a pretty precise job and hard to do well by hand.

I don't know of a chip list of IBM part numbers to standard chip numbers, but someone on the net should have one.

BTW. At one point IBM was the largest manufacturer of silicon chips in the world. Move over Texas Instruments, but alas no longer.  But as IBM used its own silicon and never sold it, it was never widely reported.


There were other specialist tools too. A PT2  was another common IBM diagnostic tool. A portable computer that folded up into a case with a separate case containing a green screen CRT. No diskette drive, but a 3M tape cartridge drive..  Woooo...  Fancy. But I can't even find a photo of that one...

Alien

 

Offline Don Hills

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Re: EEVblog #960 - Mystery Merry Mailbag Teardown
« Reply #29 on: December 27, 2016, 05:35:28 pm »
I remember when it was just CEPICS...  :)
Ah, the PT2... and the switchbox with the rows of switches and LEDs used for 3271 and other control units.

In larger systems, those PCBs plugged into backplanes. The backplane pins projected out of the back of the board for wire wrap connections as well as the traces on the backplane boards. Backplane boards were originally 4 layer (power/ground internal, signal on the surface) and later boards had 6 or 8 layers. If you had to rework, there was a special tool that fitted over the pins with cutting teeth on the end so that you could cut the trace going to a pin and then wire wrap the rework. The tool had 2 ends, you could cut just the top trace or "deep delete" and cut both the surface trace and the first internal trace. You counted the pins very carefully before cutting...   

I found a page with lots of good photos, sadly the text is Italian...
http://ummr.altervista.org/ibmtechviews.htm

 

Offline lpickup

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Re: EEVblog #960 - Mystery Merry Mailbag Teardown
« Reply #30 on: December 28, 2016, 01:08:45 am »
What a wonderful Christmas present!

I worked for IBM for 25 years (from '88-'13).  I worked in Burlington, VT in the chip design area.  It's likely the IBM chips you see in this would have been made in East Fishkill, NY, which handled the bipolar chips used by the IBM Server group, whereas Burlington handled CMOS chips, more commonly used in IBM's consumer and low-end products like the PC division, at least until the mid 90's when Fishkill eventually switched over to CMOS.  Unfortunately I have no information on the PCB layout style, but my best guess is that it did enable very early design automation.  IBM has an extremely proud EDA (Electronic Design Automation) heritage going well back before I joined (hey, when you have giant mainframes at your disposal to use, you might as well use them!) 

Well before commercial EDA tools were available, IBM had an in-house EDA group (this was the group I worked in most of my career) that wrote their own schematic entry and synthesis systems, logic simulators, transistor-level simulators, test pattern generation tools, static timing analysis, chip place and route, you name it.  And this was LONG before any of the 3rd party tool vendors existed.  And like Alien posted, at least prior to the late 80's, these all ran on mainframes accessible via terminals with very limited graphics capability.  Everything was driven by esoteric text files with a zillion three letter acronyms in addition to ALD.  This was all for chip design, but I suspect the board designers had similar technology.  When you are limited to designing on a more or less text-based display using very primitive (by today's standards) layout and routing tools, it's no wonder you'd wind up with that grid-based board design technique.

My first job at IBM was working on one of the first truly graphical EDA environments (at least for chip design).  It still ran on the mainframe and was originally written in Pascal, but it did use a 5080 graphics terminal.  A few years later we ported it to the RS/6000 UNIX environment.  This was a little after other EDA vendors were starting to have legitimate offerings on Sun, Apollo and HP machines, so we were somewhat behind the times, but most of the IBM design community was still running on mainframes.

The IBM EDA group continues to this day and certainly has its niche areas of expertise.  Cadence's Encounter Test tool is based on an IBM test tool and still has "hidden" IBM environment variables that are used for certain IBM proprietary uses (nothing outrageous, just turns on certain output formats used by custom IBM chip test equipment), and IBM's static timer is state of the art, albeit not really industry compatible (IBM's solution is the "Beta" to the industry's "VHS").  But once IBM sold its chip manufacturing business to GlobalFoundries in 2015, I wonder if the EDA group is sustainable.

One last comment to add:  at 5:56 IPL = Initial Program Load (what we would call a "boot" today).
 

Offline Brumby

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Re: EEVblog #960 - Mystery Merry Mailbag Teardown
« Reply #31 on: December 28, 2016, 10:26:34 am »
(Don't forget IMPL ... Initial Micro Program Load)
 

Offline Red Squirrel

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Re: EEVblog #960 - Mystery Merry Mailbag Teardown
« Reply #32 on: December 28, 2016, 01:24:18 pm »
That grid style kind of reminds me of how DMS cards are made.   There are different styles too, some have an actual grid (ground plane basically) while some have the regular dots.




 

Offline VK3DRB

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Re: EEVblog #960 - Mystery Merry Mailbag Teardown
« Reply #33 on: December 30, 2016, 09:46:12 am »
I worked with those types of boards for 7 years (first job out of uni) on mainframes and other equipment, at IBM.

A few points:

The diskette drive sensor is not a track sensor. It is a hole sensor in the drive that detects rotation. To be more exact, it was called a LED/PTX assembly, meaning LED and photo transistor assembly.
The PCB's of course were multi-layer, typically 8 to 12 layers. Hence the routing complexity was not difficult, especially for the autorouter. 

The DIP ICs in the plastic packages were not custom IC's. They are standard off-the-shelf IC's that were relabelled with secret IBM codes. There were a number of reasons to do this, one being IP security.

Those boards were likely reused from elsewhere. They are unlikely to be custom boards.

The edge connectors were designated in the following pattern, holding the board vertically with the components to the right:

D B
J G
P M
U S

and the pin numbers in each connector side was 2 to 13. Pin 1 did not exist in the connector.

These boards were quite expensive, as one could imagine. They were generally very reliable. The biggest problem with them was ESD. The CMOS was particularly very sensitive to ESD. The ESD may have been caused in manufacturing or packaging (latent failure) or by a service tech not handling them with the correct ESD procedures.

These boards occupied machines such as the System/32, System/34, and System/38 and a host of others.

Regarding the routing, the right angles were fine. Make no mistake, IBM has well ahead of the pack with their PCB manufacturing technology. They had no issue with etching near the corners. Most raw cards were made near the corner of Braker Lane and Burnett Road in the Balconnes area of Austin Texas, which is now a park area (not residential) due to the toxic materials that have leached into the ground. I worked next door at the IBM PCA plant on assignment, but I managed to toured the PCB plant back in 1992, courtesy of the plant manageress of the PCB plant.

Incidentally, Altium did a spiel on why 45 degree tracks are silly and that these days 90 degree tracks are fine. Sort of true. But I don't like them for the following reasons:

1. Sharp corners might invite arcing on higher voltage circuits or when an ESD spike hits.
2. They look crap. PCB layout should be impressive artwork. It looks like you've done a cheap job on a PCB. No science to it, just aesthetics. You won't get impress the chicks with 90 degree tracks. It looks like painting your fence in Mission Brown. Pride in PCB layout show the work of a craftsman rather than the average tradesman.

There is some argument about EMI. For differential high speed signals, I don't believe there is much difference between 2 x 45 degrees, or 1 x 90 degrees per track OVERALL; as long as the impedances are matched, the electrical lengths are the same etc.

I don't like right angle buses in schematic layouts. This is for a practical reason. The right angle on a bus entry or buss bends for example, "points" to the direction of its connection at the other end. Right angles do not do this. Furthermore, a poorly printed schematic is easier to decipher with 45 degree connections rather than right angles. (I hate round dots for pin 1 marks too in PCBs. Triangles are a lot smarter, for practical reasons.)  IBM's computer generated schematics were below par in my opinion - bloody hard to follow. They never used standard logic symbols for a start; just "logic blocks".
« Last Edit: December 30, 2016, 01:45:54 pm by VK3DRB »
 
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Offline lampbus

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Re: EEVblog #960 - Mystery Merry Mailbag Teardown
« Reply #34 on: December 30, 2016, 11:22:43 pm »
IPL is IBM for boot. =Initial Program Load. I did my degree placement on IBM system/36 midrange computers. I also had a System/34, which I kept in my pairents garage as it was the same size as four, four draw filing cabinets.(this beast was retired from my fathers company and I got it to learn and play with. It was stuffed with cards just like in the video.
 


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