Also, one should also read Henry Ott's paper, Partitioning and Layout of a Mixed-Signal PCB. He shows that often best way is to keep contiguous ground plane, as any slots will create voltage differences across them. Lowest ground impedance and voltage differentials between different ground points is what you want. At least in EMC tests that has been usually the winning bet
This was a point of confusion for me because there are 100 papers that say do and 100 papers that say don't. It seems like there are some major themes agreed upon, like if you do, then don't run high-speed traces across the gap. One microchip note even said do for delta-sig but don't for SAR. I haven't read the one you referenced (that I can rmember) but I will when I have time. Generally, I have found that the EMC people are the ones that usually screen don't, not sure why. My normal method of dealing with conflicting information in any science is to accept the info with the best supporting evidence. I happen to like this paper:
http://www.nxp.com/documents/application_note/AN10974.pdf
I am not going to pretend to have all the answers on that one.
Maybe I'll elaborate these issues a bit more. Somebody might be interested anyway.
As far EMC is concerned, the main philosophy is to constrain the current loops as small as possible, and minimize high-frequency ground potential differences. Only way to do that, is to build the system on as low impedance ground as possible. Adding slots adds impedance between two parts of the ground plane, thus creating voltage differences between plane points. This will act as a source voltage driving a dipole antenna if there is cables connecting each part of the plane. One needs only µA's of common-mode RF-current into cables to violate the FCC/whatever imposed limits. Thus slots are not recommended. At high frequencies, it is absolutely futile to try isolate just about anything due to fact that inductive and capacitive coupling gets out of hand. It is far better and more practical to establish a controlled path for return currents. Failure to recognize this will lead to EMI failure.
Interesting appnote from NXP. While I don't question that in that case, connecting ground planes directly leads worse ADC performance than direct connection. However, single point direct connection between planes is not good representation what happens if the plane would have been solid all the way. One would need two different boards with otherwise identical setup. At least I understood that connection was only at one point. One connection point creates huge loop (MCU is second loop point). That will certainly affect negatively the performance. BTW, how would one connect the isolated planes together using single point if there are several ADC's on the same board? How that would be handled in a system where there are several of those boards? Each ADC would like to be in the single connection point...
For ordinary two-sided boards, it actually does not matter if you cross plane splits or not, since trace width should be about same than dielectric thickness for the flux coupling (current and return current) to happen. For example, the trace impedance of a 0.2 mm wide track on 1.6 mm dielectric thickness board, yields to trace impedance of 150 ?. That is way too high for logic applications, where the impedance should be something like 50-70 ohms. For standard 4-layer board, trace width of 0.2 mm at top/bottom and reference plane (VCC/GND) in next layer, yields about 75 ohms trace impedance. If course, two sided board can work if you make the board dielectric very thin, but that is mechanically unstable solution. For OP's board buildup, I wouldn't even try to squeeze it to anything less than 4 layers. Life is difficult enough even without the signal integrity and other issues. The main DSP (especially C6000) will rule probably anything less out.
For practical evidence on my side, I have designed a board at work with 16 pieces of 65 MSPS 14-bit ADC's + FPGA & acquisition memories on the same board, and ground structure was just one solid ground plane (or, actually, the board had 8 layers of solid unbroken ground planes, and 16 layers total). Noise level was what one would expect, ±1 LSB.
Another example where I witnessed the success of solid planes were when I rebuilt the Tripath based D-class audio amplifier on a 4-layer PCB. Previous layout was two layer design, with two separate grounds, what Tripath recommended. Main problems were noise and high EMI levels, which even interfered with the radio/TV reception. Original advice was that single point grounding would be used and AGND/DGND would be connected together only at the module. However, I ended up just making a 2nd layer a solid plane on the new layout, and just placed power and small-signal components into grouped sections. Result was that the new layout was not only much more EMI quiet (I could remove almost all common-mode filtering at the inputs) but also audible noise went down hugely. Ever since, I have been very suspicious when someone recommends plane splits. Another myth I have been lately busting is that one should parallel different capacitors for more wideband result, nothing could be farther from the truth when one measures the results with a VNA...
Regards,
Janne