Author Topic: A DC power supply for 16-bit ADC  (Read 20940 times)

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Offline RayJones

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Re: A DC power supply for 16-bit ADC
« Reply #50 on: January 28, 2011, 08:23:38 am »
This is all very interesting, but spurious signals at DC (at least in our application) are dead simple to remove.

Our primary concern was fast switching signals that radiate crap everywhere, they don't even need to be on the same board.

When you deal with signals that exist in the noise, sampling purity is essential.

Perhaps a solid plane could be OK, but when it comes to prototype 8 layers boards, and hand assembly of fine pitch SMD which could cost $1000's to produce in small quantities (factoring in labour), and the need to pull 90dB of usable dynamic range, you pull every trick you know to ensure optimum performance on the first (or second) attempt.

Besides that, you did prove there is bleed beyond the end points.
Yes it is small but if you are using out of band noise, it is highly possible you could expose those small signals as spurious signals.
A cut amputates that bleed effect in a definite known manner.

Redesigning our known good PCB with a solid plane is not beneficial for us to prove it may degrade performance.
Cuts on the ground plane are so easy to place that it is hardly worth the possible "damn I wish I placed those cuts scenario".
Finally, if the chip manufacturer recommended cuts, I know I would be following their advice closer than a primitive DC test conducted in an unknown backyard.  ;)
 

Offline allanw

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Re: A DC power supply for 16-bit ADC
« Reply #51 on: January 28, 2011, 09:43:50 am »
I think I saw the same test in one of Howard Johnson's signal integrity videos.
 

Offline jahonen

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Re: A DC power supply for 16-bit ADC
« Reply #52 on: January 29, 2011, 04:09:32 am »
I agree on the point that usually one does not experiment with expensive prototype boards. I was certainly not suggesting that anybody should re-design a working board based on my experiments. I wouldn't trust a comment from a random forum from somebody completely unknown either. Instead, my experiment was meant for food of thought. Yes, it most certainly does bleed measurably between p5-p6. But between p6-p7 there was no measurable voltage (below 1 µV). That indicates that most current is concentrated near point I1. Plane resistance is not trivial to calculate, thus it is difficult to estimate the resistive coupling without measuring.

I do very well know that higher frequency signals have other sometimes very bizarre coupling ways, like mutual inductance, which is naturally completely absent in case of DC. Inductive coupling is perhaps the most difficult mechanism. Only way to reduce that is to reduce the area between signal and ground and increase distance between two signal loops. However, skin depth dictates that for example at 30 MHz, skin depth is about 12 µm. One could then even put different high frequency signals in each side of the plane and still get almost no cross-coupling. That would also suggest that for high frequencies, splits are not so effective, since coupling could be due to something else than due to the IR drop of aggressor signal. RF guys usually add more grounding or shielding if they need more isolation between signals, I do not know if anyone there uses splits to reduce coupling.

That's why I am also going to do some experiments in the AC domain using a spectrum analyzer with a tracking generator, like I thought above. I'm not personally completely convinced that primary noise coupling mechanism for higher frequencies is through galvanic connection via the ground plane. If it is some other form of coupling, then the slot might possibly cause things to be worse unless the effect is understood. Another thing is that if the chip has two different ground connections, it is usually stated that they should be at the same potential. Now, better the split is, bigger the difference between potentials of these two grounds, thus inter-gnd current (like common-mode) flows through the chip. My primary interest is to understand the coupling mechanisms via measurements, so I can better understand what is the dominant mode of coupling and how much, by what means and where I can degrade the shielding in case of cost reduction situation and still get acceptable results. It also enables to optimize right things in case of performance maximization. It might also well turn out that either is acceptable if properly implemented, i.e. no dramatic difference between these two school of thoughts (my best guess is this).

What also bothers me, is that the "split ground"-chapter in ADC/DAC datasheets seems to be copy&paste'd for decades from one datasheet to another without anyone bothering to actually make measurements and evaluate the results for both ground methods, especially evaluating the external interference immunity. That would be much more convincing than just simple chapter of old statements. Datasheets are not unfortunately always based on physical facts, but industry practices. Although I have been getting impression that newer datasheets do not unconditionally recommend splitting so often, instead they will emphasize the correct parts placement. It is a bit like of "Faraday cage"-advice that is certainly useless unless you know that direct radiation from the circuit in it is the actual source of problem. Usually, it is the common mode ground voltage induced currents in cables what cause EMI failures, rarely the circuit board itself. If all signals entering/exiting the cage are not filtered at the edge, they will conduct the noise outside with ease, thus the cage won't improve the situation at all.

Finally, ADS5485EVM seems to be using single unified ground plane, and still achieving good results. The statement about grounding seems to be reversed: "The layout features a common ground plane; however, similar performance can be obtained with careful layout using a split ground plane." I can't believe that two different ADC's obey different set of laws of electromagnetism. Same seems to be the case with ADI AD9650/AD9268/AD9258/AD9251/AD9231/AD9204/AD9269/AD6659 evaluation board.

Regards,
Janne

This is all very interesting, but spurious signals at DC (at least in our application) are dead simple to remove.

Our primary concern was fast switching signals that radiate crap everywhere, they don't even need to be on the same board.

When you deal with signals that exist in the noise, sampling purity is essential.

Perhaps a solid plane could be OK, but when it comes to prototype 8 layers boards, and hand assembly of fine pitch SMD which could cost $1000's to produce in small quantities (factoring in labour), and the need to pull 90dB of usable dynamic range, you pull every trick you know to ensure optimum performance on the first (or second) attempt.

Besides that, you did prove there is bleed beyond the end points.
Yes it is small but if you are using out of band noise, it is highly possible you could expose those small signals as spurious signals.
A cut amputates that bleed effect in a definite known manner.

Redesigning our known good PCB with a solid plane is not beneficial for us to prove it may degrade performance.
Cuts on the ground plane are so easy to place that it is hardly worth the possible "damn I wish I placed those cuts scenario".
Finally, if the chip manufacturer recommended cuts, I know I would be following their advice closer than a primitive DC test conducted in an unknown backyard.  ;)

« Last Edit: January 29, 2011, 04:40:20 am by jahonen »
 

Offline CafeLogic

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Re: A DC power supply for 16-bit ADC
« Reply #53 on: January 29, 2011, 04:39:12 am »

Finally, ADS5485EVM seems to be using single unified ground plane, and still achieving good results. The statement about grounding seems to be reversed: "The layout features a common ground plane; however, similar performance can be obtained with careful layout using a split ground plane." I can't believe that two different ADC's obey different set of laws of electromagnetism.


LOL, now I am sure you can understand my original statement about it being a point of confusion.
 

Offline jahonen

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Re: A DC power supply for 16-bit ADC
« Reply #54 on: January 29, 2011, 04:50:16 am »

Finally, ADS5485EVM seems to be using single unified ground plane, and still achieving good results. The statement about grounding seems to be reversed: "The layout features a common ground plane; however, similar performance can be obtained with careful layout using a split ground plane." I can't believe that two different ADC's obey different set of laws of electromagnetism.


LOL, now I am sure you can understand my original statement about it being a point of confusion.

That's why my bet is on that it does not make a huge difference performance-wise, if properly implemented. If either would be significantly better for performance and in all cases, then that particular one would be unanimously recommended solution. Probably even the chip manufacturers can't decide which one to recommend.

Regards,
Janne
 

Offline RayJones

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Re: A DC power supply for 16-bit ADC
« Reply #55 on: January 29, 2011, 08:38:28 am »
Yeah without being a particle physicist there is a lot of gut feeling in the whole process.

We actually stitched together the individual split plane edges with a fence of vias along the edge as prior design work with analog filters and a network analyser revealed the nominal grounds on top and bottom layers of the board would allow signals above a GHz or so back into the passband
If we connected them together with solder braid around the edge, the response returned to that expected.
It would appear that they were not actually as solid as they seemed and looked.
Whether this was truly detrimental or not was certain, but given we were using the filter in a radar receiver that has pulsed RF in the 100's kW range floating about we felt it was better to keep it out.

One thing we all agree on though us never run digital signals, or any other for that matter, across the analog input section as the induced return currents that hug close below the trace are what we are aiming to avoid with either a solid or split plane.
 

Offline saturation

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Re: A DC power supply for 16-bit ADC
« Reply #56 on: January 30, 2011, 02:16:44 am »
Excellent posts as always, jahonen.
Best Wishes,

 Saturation
 

Offline jahonen

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Re: A DC power supply for 16-bit ADC
« Reply #57 on: February 03, 2011, 03:24:27 am »
After some thinking, I thought that maybe I'll use some kind of noisy digital chip to generate the noise, instead of simple two transmission line crosstalk experiment. So I decided to put a crystal oscillator driving a clock fan-out buffer which drives 4 pieces of 15 cm long ~50-ohm terminated transmission lines (transmission line lengths are precisely matched). The victim trace is a 15 cm long (also matched) transmission line, with a SMA connector at the other end, so I can easily connect it to the spectrum analyzer, which should give a sensitivity below 1 µV. I expect something like 10-50 MHz oscillator to generate rich harmonics, which should be quite easy to detect. Clock buffers are usually quite noisy, thus it is used.

Here are the layouts of the boards with I intend to experiment next, to compare two "schools of thought". Design is a 4-layer board, what one could use ordinarily. 2nd layer is solid ground, 3rd layer is VCC and bottom is also solid ground. The boards are exactly identical except board "B" has a 6.5 mm wide void gap in all layers between "analog" and digital sections, except for small bridge at the left edge. Via fences are placed in moat edges of both sections.

I'll have to wait until we dispatch a group hobby PCB order at my work, but as soon as I get the boards, assemble them and do the measurements, I'll report my findings here. It will be interesting to quantitatively measure the difference (at least for me).

Regards,
Janne
 

Offline CafeLogic

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Re: A DC power supply for 16-bit ADC
« Reply #58 on: February 03, 2011, 03:39:51 pm »
Looks awesome, looking forward to the results.
 

Offline scrat

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Re: A DC power supply for 16-bit ADC
« Reply #59 on: February 04, 2011, 02:35:46 am »
Yes, should be 100dB, theoretically, since the input to output gain is -50dB for noise.
One machine can do the work of fifty ordinary men. No machine can do the work of one extraordinary man. - Elbert Hubbard
 

Offline jahonen

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Re: A DC power supply for 16-bit ADC
« Reply #60 on: March 18, 2011, 06:46:26 am »
Update on this thing, got the PCB's and assembled them today. I'll try to make measurements tomorrow. Picture of the test boards attached.

Regards,
Janne
 

Offline scrat

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Re: A DC power supply for 16-bit ADC
« Reply #61 on: March 18, 2011, 12:35:32 pm »
You have not stated the sampling rate you are using?

If using a high sample rate, you may also wish to ensure the clock used for sampling is also ultra stable. This may require a separate supply just for the clock generator.

The best way to evaluate you noise performance is to capture 2^n samples eg 1024. then perform an FFT on the results.
This will reveal if you have any spurious signals getting in there, degrading performance.
Even better to reveal spurious signals is to average multiple FFT's over time.

Simply seeing one digit of noise is not always indicative of a good sampler.  :'(

Thanks. The sampling rate is 10 MSPS.

Let's say the PSRR of an adjustable LDO linear regulator is 50dB. If two such linear regulators are cascaded in series, what will be the effective PSRR? Is it 100dB?

Yes, should be 100dB, theoretically, since the input to output gain is -50dB for noise.

Having seen an update on the thread, I now realize I was answering a question posted a few pages before :( ... And what a few pages I was missing! Very interesting and high level discussion.  I apologize for my last post.

BTW, I look forward to the results of the experiments.
One machine can do the work of fifty ordinary men. No machine can do the work of one extraordinary man. - Elbert Hubbard
 

Offline jahonen

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Re: A DC power supply for 16-bit ADC
« Reply #62 on: March 18, 2011, 06:45:53 pm »
Okay, I have performed the measurements. Units are dBµV, so that 0 dB is 1 µV, 20 dB = 10 µV etc. Result seems to be that neither is very good :) I can only draw conclusion that there are much more dominant coupling and resonance modes involved here than just the IR drop in the ground plane. And of course that it is difficult to predict the result before you go and measure the result.

One with the split has about 2 dB less coupling in lower harmonics, but 8 dB higher coupling in some high harmonic (15th I believe, fundamental is 12.288 MHz). Also, there seems to be some kind of a resonance around 300-400 MHz in the board with no split.

If we compare the coupling to the 16-bit ADC with full-scale range of +-1 V, then 1 LSB is about 30 µV, which is 30 dBµV (26 dBµV if we account for RMS value). Comparing that to what I measured, the coupling does not reach this level until above 100 MHz for both cases. Of course it depends what kind of application one has, time domain or frequency domain application.

Regards,
Janne
 

Offline scrat

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Re: A DC power supply for 16-bit ADC
« Reply #63 on: March 19, 2011, 02:19:09 am »
It seems like at low frequencies the return current uses a wide portion of the ground plane, while this doesn't happen in the high range. Also, the plane is acting as a screen (at high freq), maybe letting currents loops to close and oppose to the generated field, and the split cuts those loops.
This is my interpretation. I know it's too easy to say now, but I would have guessed right, when I thought about the board. :)

The situation is maybe a little far from a real board, IMHO, since there you have signals which must cross the boundaries between two different gnd domains, too.
One machine can do the work of fifty ordinary men. No machine can do the work of one extraordinary man. - Elbert Hubbard
 

Offline RayJones

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Re: A DC power supply for 16-bit ADC
« Reply #64 on: March 19, 2011, 08:17:21 am »
Hi Jahonen,

I'm a bit bemused by your solid ground plane board.
You included the "via fences".

Without going back, my memory is that you are proposing the use of splits is unnecessary, but the via fence is used to bond the edge of the splits to avoid radiating from each plane.

May I suggest you have tested a hybrid?
Perhaps the resonance is an effect of the two fences interacting, C between the planes, L between the fences.

You could drill out all the via's, but it still would not be a solid plane due to all the remaining holes.

 

Offline scrat

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Re: A DC power supply for 16-bit ADC
« Reply #65 on: March 20, 2011, 12:18:10 am »
Hi Jahonen,

I'm a bit bemused by your solid ground plane board.
You included the "via fences".

Without going back, my memory is that you are proposing the use of splits is unnecessary, but the via fence is used to bond the edge of the splits to avoid radiating from each plane.

May I suggest you have tested a hybrid?
Perhaps the resonance is an effect of the two fences interacting, C between the planes, L between the fences.

You could drill out all the via's, but it still would not be a solid plane due to all the remaining holes.

The plane is almost continuous, those vias are so small holes that you wouldn't mind until you reach several GHz (@1GHz, wavelength into FR4 is > 130mm, into air it's about 300mm). I don't know why he decided to put them there, but since there are so many vias, the upper flood is almost uniformly stitched to the bottom plane around the board.

BTW, in my previous post I didn't congratulate with Janne. It's amazing the work he's done only for the will of experimenting this single fact!
One machine can do the work of fifty ordinary men. No machine can do the work of one extraordinary man. - Elbert Hubbard
 

Offline jahonen

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Re: A DC power supply for 16-bit ADC
« Reply #66 on: March 20, 2011, 03:18:14 am »
I decided to put the vias in hope that it would block power plane radiating directly to victim side of the test board. On second thought, this might not have been entirely successful strategy.

Yes, it can be called an hybrid. But for the frequencies we are dealing in here, I think it can be considered as solid. What I have heard from my friend who works with mobile phone base station etc. RF-things (LNA's in the mast etc.), they seem to put ground vias just about anywhere if they want to increase the isolation. They must optimize the noise coupling into their RF-signal, and the specs are typically very strict. I asked if they use splits to isolate the control side, and the answer was no. Thus the large via count. But it is certainly true that usually they do not exist in split edges in typical designs.

As for explanation for resonances, I just thought that maybe it is not radiation of the signals which seem to cause excessive crosstalk at higher frequencies, but VCC layer capacitor. My current guess is that VCC plane capacitor return current travels top/bottom sides of the board, coupling the noise to victim trace side, swamping out ground noise. VCC layer has also a big slotted hole due to all those ground vias, creating a big loop (which may cause resonances). In split board, this loop does not exist, as the all the planes have been cleared. Fortunately, this loop is relatively easy to cut (only two narrow bridges exist at each side of the board). So more testing is in order, I think.

Here are the images of GND and VCC layers attached from CAM350.

Regards,
Janne
« Last Edit: March 20, 2011, 05:46:53 am by jahonen »
 

Offline RayJones

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Re: A DC power supply for 16-bit ADC
« Reply #67 on: March 20, 2011, 02:54:27 pm »
Ahhh, the "hidden" power plane.

I'd definitely try cutting in at the edge of board at the bottom row of vias, thus isolating the VCC plane entirely.
If you could, you should even try tying the floating copper to ground (easier at the PCB design level than post production)

You wouldn't route stray digital signal lines over your analog input, likewise a full slot absolutely isolates noisy impulse currents from the power plane.

This then returns back to the original question, slot or no slot on the ground plane.
The logical extension is if you control the radiation from the power plane with a slot, should not also do so for the other half, the ground plane?

Get more intriguing, keep on trying!

 

Offline jahonen

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Re: A DC power supply for 16-bit ADC
« Reply #68 on: June 15, 2011, 03:11:59 am »
Sorry for late reply but here are the results with VCC plane cut. I also reduced the attenuation on the spectrum analyzer to minimum, to reduce the noise floor.

It seems that the noise is dramatically reduced for both cases when VCC plane is cut. Coupling must have therefore been due to PCB antipad-plane capacitance. There seems to be some advantage (maybe 2-5 dB at best) for the slot, after all, but then, it is considerably worse in narrow frequency region, between 500 and 600 MHz, as you can see (last image shows the "advantage" of the slot, bigger number is better).
There seems to be bigger advantage on even harmonics, but I guess that is not real effect in PCB, but a duty cycle variation between two different oscillators and clock skew variations on the clock buffer.

It is therefore verified that digital power supply planes should not be poured in analog section, careful filtering is required in between.

Regards,
Janne
 


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