Author Topic: Should ICs always be packaged in ESD safe bags?  (Read 4740 times)

0 Members and 1 Guest are viewing this topic.

Offline DTJTopic starter

  • Frequent Contributor
  • **
  • Posts: 997
  • Country: au
Should ICs always be packaged in ESD safe bags?
« on: July 24, 2017, 07:30:14 am »
I got some ICs from RS and they appear to be in a plain old PE plastic bag rather than the expected metalised foil or even the non-ESD generating pink plastic bag.

I'd assume RS know what they are doing.

Are some ICs sufficiently immune to ESD to be packed like this?
 

Offline Ian.M

  • Super Contributor
  • ***
  • Posts: 12860
Re: Should ICs always be packaged in ESD safe bags?
« Reply #1 on: July 24, 2017, 07:50:04 am »
RS product page: http://uk.rs-online.com/web/p/temperature-humidity-sensors/8937118/
If you look in the datasheet you'll find it has a 4KV ESD rating (HBM).  That puts it in class 3A of ESD STM5.1-1998.  There's only one class less sensitive: class 3B (>8KV HBM ESD rating).
 
The following users thanked this post: Silveruser

Offline wraper

  • Supporter
  • ****
  • Posts: 16865
  • Country: lv
Re: Should ICs always be packaged in ESD safe bags?
« Reply #2 on: July 24, 2017, 08:51:09 am »
That bag may be ESD dissipative. If it was inside another ESD shielding bag, it might be OK. Otherwise it's not.

RS product page: http://uk.rs-online.com/web/p/temperature-humidity-sensors/8937118/
If you look in the datasheet you'll find it has a 4KV ESD rating (HBM).  That puts it in class 3A of ESD STM5.1-1998.  There's only one class less sensitive: class 3B (>8KV HBM ESD rating).
4kV HBM rating is not much at all. Rarely any IC goes below 2kV HBM.
FYI there is also
IEC 61000-4-2 level 4:
– 15 kV (air discharge)
– 8 kV (contact discharge)



8kV contact discharge is way stronger than 8kV HBM. 10kV HBM is weaker than 2kV IEC 61000-4-2
https://www.onsemi.com/pub/Collateral/TND410-D.PDF
Quote
While HBM is usually sufficient for the controlled ESD environment of the factory floor, it is completely inadequate for
system level testing. The levels of ESD strikes, both the voltages and the currents, can be much greater in the end
user environment. For this reason, the industry uses a different testing standard for system level ESD testing. This
standard is known as the IEC 61000-4-2.
« Last Edit: July 24, 2017, 09:00:58 am by wraper »
 

Offline Ian.M

  • Super Contributor
  • ***
  • Posts: 12860
Re: Should ICs always be packaged in ESD safe bags?
« Reply #3 on: July 24, 2017, 09:09:46 am »
System level ESD testing standards are totally irrelevant for a loose IC before its soldered to a board.

However I wouldn't entirely trust RS components' choices for individual part or small multipack packaging when it comes to ESD sensitivity. Historically, I've seen quite a few logic chips and similar ICs that they've repackaged in packages that don't appear to offer any ESD protection whatsoever. 
 

Offline wraper

  • Supporter
  • ****
  • Posts: 16865
  • Country: lv
Re: Should ICs always be packaged in ESD safe bags?
« Reply #4 on: July 24, 2017, 09:30:05 am »
System level ESD testing standards are totally irrelevant for a loose IC before its soldered to a board.
Didn't you know that HBM test is not done on a bare IC as well?  :palm: EDIT: BTW many parts claim IEC 61000-4-2 compliance at the component level.
Like this HDMI switch:
http://www.ti.com/lit/ds/symlink/tmds361b.pdf
Quote
IEC 61000-4-2(6), contact discharge ±8,000
IEC 61000-4-2(6), air discharge ±15,000
You said:
Quote
That puts it in class 3A of ESD STM5.1-1998.  There's only one class less sensitive: class 3B (>8KV HBM ESD rating).
By this you made a false impression this is nearly as robust device as you may get while in reality it's not.




« Last Edit: July 24, 2017, 09:50:49 am by wraper »
 

Offline Ian.M

  • Super Contributor
  • ***
  • Posts: 12860
Re: Should ICs always be packaged in ESD safe bags?
« Reply #5 on: July 24, 2017, 10:00:57 am »
Didn't you know that HBM test is not done on a bare IC as well?  :palm:
It may not be industry best practice but the manufacturer's datasheet for the O.P's chip (TSYS01) specifies its ESD sensitivity in terms of the HBM test applied pin-to-pin.  :popcorn:
 

Offline wraper

  • Supporter
  • ****
  • Posts: 16865
  • Country: lv
Re: Should ICs always be packaged in ESD safe bags?
« Reply #6 on: July 24, 2017, 10:15:29 am »
Didn't you know that HBM test is not done on a bare IC as well?  :palm:
It may not be industry best practice but the manufacturer's datasheet for the O.P's chip (TSYS01) specifies its ESD sensitivity in terms of the HBM test applied pin-to-pin.  :popcorn:
It means they put the current between pins. They do connect it to the circuit, not just strike it free floating, which was the point of my post.
 

Offline wraper

  • Supporter
  • ****
  • Posts: 16865
  • Country: lv
Re: Should ICs always be packaged in ESD safe bags?
« Reply #7 on: July 24, 2017, 10:33:00 am »
To better word it, by bare IC I was meaning IC by itself, without a circuit connected. Connection to the test circuit is not necessarily is done by soldering. The same applies to both HBM and IEC 61000-4-2.
 

Offline DTJTopic starter

  • Frequent Contributor
  • **
  • Posts: 997
  • Country: au
Re: Should ICs always be packaged in ESD safe bags?
« Reply #8 on: July 24, 2017, 10:41:47 am »
RS product page: http://uk.rs-online.com/web/p/temperature-humidity-sensors/8937118/
If you look in the datasheet you'll find it has a 4KV ESD rating (HBM).  That puts it in class 3A of ESD STM5.1-1998.  There's only one class less sensitive: class 3B (>8KV HBM ESD rating).

Ok I guess that explains it.
I looked in the data sheet and saw the 4kV ESD rating but without the required knowledge it did not help me.

It wasn't in any other packaging - just the usual white paper bag stuffed full of parts.
 

Offline wraper

  • Supporter
  • ****
  • Posts: 16865
  • Country: lv
Re: Should ICs always be packaged in ESD safe bags?
« Reply #9 on: July 24, 2017, 10:49:41 am »
Ok I guess that explains it.
No it doesn't. It's still remains an ESD sensitive part with all handling precautions still applying.
« Last Edit: July 24, 2017, 10:54:23 am by wraper »
 

Offline DTJTopic starter

  • Frequent Contributor
  • **
  • Posts: 997
  • Country: au
Re: Should ICs always be packaged in ESD safe bags?
« Reply #10 on: July 24, 2017, 10:51:42 am »
Ok I guess that explains it.
No it doesn't. It's still remains an ESD sensitive part with all handling precautions still applying.


Of course normal handling precautions apply.  :-+
 

Offline wraper

  • Supporter
  • ****
  • Posts: 16865
  • Country: lv
Re: Should ICs always be packaged in ESD safe bags?
« Reply #11 on: July 24, 2017, 10:54:38 am »
My guess would be that some idiot had read that it is a temperature sensor (like PTC, NTC, RTD) and entered into their system as it is handled it as such. Without noticing the fact it is IC and ESD sensitive.
 

Offline wraper

  • Supporter
  • ****
  • Posts: 16865
  • Country: lv
Re: Should ICs always be packaged in ESD safe bags?
« Reply #12 on: July 24, 2017, 11:03:59 am »
Somewhat related. I have received some moisture sensitive parts from RS. There was no any moisture sensitive bag, desiccant, humidity indicator card or MSL marking and shelf life before baking required on the package. On the contrary, Farnell and Mouser have always done this properly. Even TME with their not so perfect handling practice do this as well.
 

Offline DTJTopic starter

  • Frequent Contributor
  • **
  • Posts: 997
  • Country: au
Re: Should ICs always be packaged in ESD safe bags?
« Reply #13 on: July 24, 2017, 11:22:54 am »
Somewhat related. I have received some moisture sensitive parts from RS. There was no any moisture sensitive bag, desiccant, humidity indicator card or MSL marking and shelf life before baking required on the package. On the contrary, Farnell and Mouser have always done this properly. Even TME with their not so perfect handling practice do this as well.


I had wondered the same about it being treated as a sensor. The manufacturer (TE) seem to refer to it as a TSYS01 in all their data sheets and documentation. I didn't think RS sold them as searching for TSYS01 in their system returns no hits. Previous stock was from a smaller company and they supplied them in a cut down ESD tube in an metalised bag.


Farnell are also good in that they'll 'minireel' a lot of semis for no fee.
 

Offline wraper

  • Supporter
  • ****
  • Posts: 16865
  • Country: lv
Re: Should ICs always be packaged in ESD safe bags?
« Reply #14 on: July 24, 2017, 11:30:53 am »
Farnell are also good in that they'll 'minireel' a lot of semis for no fee.
AFAIK it's no longer the case. They reduced minimum quantity required but introduced a fee.
 

Offline DTJTopic starter

  • Frequent Contributor
  • **
  • Posts: 997
  • Country: au
Re: Should ICs always be packaged in ESD safe bags?
« Reply #15 on: July 24, 2017, 12:36:34 pm »
Farnell are also good in that they'll 'minireel' a lot of semis for no fee.
AFAIK it's no longer the case. They reduced minimum quantity required but introduced a fee.


ah ok, bummer. Worked for me 3 months ago.
 

Offline madires

  • Super Contributor
  • ***
  • Posts: 7765
  • Country: de
  • A qualified hobbyist ;)
Re: Should ICs always be packaged in ESD safe bags?
« Reply #16 on: July 24, 2017, 12:52:59 pm »
Doesn't each ESD event have the potential to weaken the ESD protection?
 

Offline wraper

  • Supporter
  • ****
  • Posts: 16865
  • Country: lv
Re: Should ICs always be packaged in ESD safe bags?
« Reply #17 on: July 24, 2017, 02:06:28 pm »
Doesn't each ESD event have the potential to weaken the ESD protection?
Yes it does. HBM uses only one pulse of each polarity. But IEC 61000-4-2 test uses minimum 3 pulses of each polarity because damage can accumulate until part fails.

Quote
Another difference between the HBM and IEC standards is the number of strikes used during testing. The HBM
standard requires only a single positive and single negative strike to be tested, whereas the IEC 61000-4-2 test requires
3 positive strikes and 3 negative strikes. It is possible for a device to survive the first strike, but fail on subsequent
strikes due to damage sustained during the initial strike. In today’s application environment, systems can be subject to
many strikes over their lifetimes, and it is becoming more common for system vendors to test their systems with even
more strikes than the minimum of three that are specified in the IEC 61000-4-2 standard.
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf