Author Topic: openvizsla......... still......  (Read 28275 times)

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Offline Smokey

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openvizsla......... still......
« on: May 15, 2013, 09:57:54 am »
I don't think any hardware forum section dedicated to crowd funding would really be complete without talking about openvizsla at least a little bit. 
http://www.kickstarter.com/projects/bushing/openvizsla-open-source-usb-protocol-analyzer?ref=card

Asked for $17500..... Raised $81025.... 463%..... on Dec 22, 2010.... People are still waiting....

What happened?  From what I can tell they got in way over their head technically and instead of getting help they just kept floundering.... for years.....  Then they mostly stopped communicating with the backers or anyone.  No updated for long periods of time.  Their twitter feed which they linked has... 0.... posts.  The updates they did release showed the silly amateur PCB mistakes that would have never gotten past a real design review.  I guess when they said "we certainly have enough peer review within our team (of highly experienced embedded and EE experts)"  they must have been printing their own business cards.  It appears like they are still working on something, but all the updates are private.

What can we learn from this?  If you are not just running a scam and you take people's money you better be sure you can deliver what you say you are going to deliver.  Plus it's stupid to call something open source if you aren't going to... well... open the source from the beginning.  Just look at this forum.  Someone posts a schematic and within hours has the feedback of a handful of professional engineers.  For free.  It's one thing if you are going to make a product and sell it closed, but if you are going to advertize as open then why not take full advantage of the community that comes along with an open project.

I love this last comment (May-9-2013):
"According to the U.S. BLS my $250 in 2010 dollars is now worth $266.87. If I had invested that in Google on Dec 22, 2010 I would have $362. If I had flushed that money down the toilet I'd have the same thing I have right now."
 

Offline EEVblog

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Re: openvizsla......... still......
« Reply #1 on: May 15, 2013, 10:05:59 am »
I believe that "bushing" who ran the campaign is the same person as on this fourm. i.e. the one who originally did the Rigol hack.
 

Offline Rasz

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Re: openvizsla......... still......
« Reply #2 on: May 15, 2013, 12:06:55 pm »
The sad thing is this project was attractive in 2010, it was still attractive in 2011, in 2012 it became redundant (3.0 became ubiquitous), and today it would be an outdated toy.
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Offline swSteve

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Re: openvizsla......... still......
« Reply #3 on: May 28, 2013, 07:20:13 pm »

Hi

Wouldn't a USB2.0 analyzer unit still be useful since
even USB3 devices of interest
could be tested while connected to a USB2 host?

Steve
 

Offline Rasz

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Re: openvizsla......... still......
« Reply #4 on: May 28, 2013, 07:48:01 pm »

Hi

Wouldn't a USB2.0 analyzer unit still be useful since
even USB3 devices of interest
could be tested while connected to a USB2 host?

Steve

Give me an example of 3 devices you would need to debug USB 2.0 communications today (and its impossible to do in virtual machine or using Wireshark/USBlyzer).
I can come up with only one (new kinect at the end of the year) and it will be USB 3.0 only.
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Offline tinhead

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Re: openvizsla......... still......
« Reply #5 on: May 28, 2013, 09:22:14 pm »
What can we learn from this? 

actually nothing else than "don't spend money on projects ran by hobby hackers"
I spend money as well on that thing, mostly because of this statement
"We have been working on this project in various forms for over two years now, and large parts of the
hardware design have already been proven"


Unfortunately it was not the truth, they bought first Altium licenses, then (instead spend money on proper
training) tried to design multiple times proto PCBs, then changed design (why?) designed once again something else,
announced "ohh, we can capture usb data frame" (what a joke, really, after a year of development? for world best hackers?)
lied about "wriong produced PCBs" (yeah, multilayer is not for hobby pseudo EEs, you need to know what you doing).

Even lied about "we have send proto to top backers, actually nobody from them in EU recieved every a proto PCB.
I wondering only why nobody started to screem already here, or was it simply the fact that bushing disapered?

They (bushing and pytey as well) are not even fair enough to say "f*, we have no money", not even to send the
protos (they posted 4 months agon protos beeing produced .. so where they are?) to backers, not even
to post cad or other project files.

The only good thing is, bushing (when not in jail) is from time to time on CCC events, so there is a good and
real chance to catch his ass.
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Offline desowin

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Re: openvizsla......... still......
« Reply #6 on: May 28, 2013, 09:57:52 pm »
Give me an example of 3 devices you would need to debug USB 2.0 communications today (and its impossible to do in virtual machine or using Wireshark/USBlyzer).

On Windows you can use USBPcap to capture logs to analyze later in Wireshark. So no excuses for lack of open-source tool to do that in Windows!

http://desowin.org/usbpcap

As a side note, the USB implementation in DigiTech RP250 is horribly broken and it doesn't work in virtual machines.

I am the backer of openvizsla as well...
 

Offline firewalker

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Re: openvizsla......... still......
« Reply #7 on: May 29, 2013, 12:23:55 am »
On another thread (mu camera) someone had posted pcb photos an prototypes the the project came up.

Alexander.
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Offline firewalker

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Offline marcan

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Re: openvizsla......... still......
« Reply #9 on: May 29, 2013, 06:39:46 am »
As one of bushing's friends, I can at least vouch that he not a scammer, nor has he benefited personally from the project (in fact he's volunteered a significant amount from his personal savings).

The last news I heard is that the developers have received the (final revision) boards and are working on the firmware for them.

This project may have been a significant trainwreck the way it was managed, but it is not a scam, nor is it dead.
 

Offline swSteve

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Re: openvizsla......... still......
« Reply #10 on: May 29, 2013, 02:43:47 pm »

Marcan

I'm a US-based $1K backer of OV and I've received nothing.

After promising openness they kept the entire code-base and hardware secret.

What are we supposed to think?


Smart people are being denied the chance to help out.

why?
 

Offline EEVblog

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Re: openvizsla......... still......
« Reply #11 on: May 29, 2013, 05:06:22 pm »
Smart people are being denied the chance to help out.
why?

Well, from that aspect I can understand.
When you run a public campaign (or blog  ;) ) you have to very careful about accepting offers of help, as generous and genuine as they may be.
Even the best "experts" can come in and completely ruin things, waste your time, take you in wrong directions etc.
Ask 10 "experts" for advice on something technical and you'll likely get 10 different answers.
 

Offline swSteve

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Re: openvizsla......... still......
« Reply #12 on: May 29, 2013, 05:28:05 pm »
I can see what you're talking about. But this project was sold as open.

Meanwhile I was referring to the free peer review mentioned
In the first post of this thread.


I would not have contributed had they promoted it as a closed project.

That part was an outright lie.
 

Offline BravoV

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Re: openvizsla......... still......
« Reply #13 on: May 29, 2013, 05:37:32 pm »
As one of bushing's friends, I can at least vouch that he not a scammer, nor has he benefited personally from the project (in fact he's volunteered a significant amount from his personal savings).

The last news I heard is that the developers have received the (final revision) boards and are working on the firmware for them.

This project may have been a significant trainwreck the way it was managed, but it is not a scam, nor is it dead.

As a good gesture, mind ask him to say a few words here since he is also a member in this forum, and we got few backers here as well.

Offline Rasz

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Re: openvizsla......... still......
« Reply #14 on: May 29, 2013, 06:14:18 pm »
Well, from that aspect I can understand.
When you run a public campaign (or blog  ;) ) you have to very careful about accepting offers of help, as generous and genuine as they may be.
Even the best "experts" can come in and completely ruin things, waste your time, take you in wrong directions etc.
Ask 10 "experts" for advice on something technical and you'll likely get 10 different answers.

On the other hand  there are those gold binding posts :) You cant know everything, and when you are struggling its better to ask for help than just sit on your ass (or on backers money).
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Offline EEVblog

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Re: openvizsla......... still......
« Reply #15 on: May 29, 2013, 08:04:58 pm »
I can see what you're talking about. But this project was sold as open.

An "open" project does not have to be open during the development process, only when complete. (unless they specifically promised otherwise?)
There can in fact be big downsides to going open during the design process, as I can well attest to with my PSU series. You end up with a thousand people screaming at you to do it this way, do it that way, asking questions and demanding things which start getting you off track etc.
 

Offline EEVblog

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Re: openvizsla......... still......
« Reply #16 on: May 29, 2013, 08:09:49 pm »
On the other hand  there are those gold binding posts :) You cant know everything, and when you are struggling its better to ask for help than just sit on your ass (or on backers money).

Sure, but maybe they thought they didn't need help.

Notice I did not mention what the connectors are for, because when people know, that's when the flood of alternative suggestions start rolling in...
And if you run a project open like this, that can easily lead to derailing of a project.
 

Offline ddavidebor

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openvizsla......... still......
« Reply #17 on: May 29, 2013, 08:45:28 pm »
What are that connector for?

XD
Davide Bortolami,
Fermium LABS srl
 

Online Andy Watson

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Re: openvizsla......... still......
« Reply #18 on: May 29, 2013, 09:04:22 pm »
I can see what you're talking about. But this project was sold as open.
.... You end up with a thousand people screaming at you to do it this way, do it that way, asking questions and demanding things which start getting you off track etc.
Ben and Phil have demonstrated that they are quite capable of ignoring any amount of screaming. They could have published the design for peer review and still ignored the replies (there are only 580 backers, not thousands). I backed this project because it was billed as "open", it's in the title of the project! As Smokey pointed out in the OP, they made silly mistakes which could easily have been picked up by the more knowledgeable backers (of which there are many). Once could be described unfortunate, but we are now on at least the third major revision of the PCB.

If as Marcan suggests, the "final" revision boards have been delivered and are being worked on, why hasn't Ben reported this on the project website or group forum. I do not believe Ben and friends are scammers but without a plausible explanation for all the secrecy it is very hard to give any credibility to their excuses.
 

Offline EEVblog

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Re: openvizsla......... still......
« Reply #19 on: May 29, 2013, 09:48:33 pm »
Ben and Phil have demonstrated that they are quite capable of ignoring any amount of screaming.  They could have published the design for peer review and still ignored the replies (there are only 580 backers, not thousands).

How can you know that? Just because they don't reply much? That's no indication at all I can assure you.
And someone who is constantly on the receiving end of this I can assure you it doesn't take much (or many people) to get you down, questioning yourself and your work, putting oyu off track, wasting your time etc etc.
Unless you have been in this position it's hard to understand.

Quote
I backed this project because it was billed as "open", it's in the title of the project!

Like I said, that does not have to extend to the design process.
If you think it does/should, then that's just your opinion and assumption.
Unless they specifically said they would share the info during the design process, then you can't just automatically assume they would do that.
And like I  said again, there can be good reason not share that info unless it's released or close to released. Many OSHW people do not release info until the project is finished.

Quote
As Smokey pointed out in the OP, they made silly mistakes which could easily have been picked up by the more knowledgeable backers (of which there are many). Once could be described unfortunate, but we are now on at least the third major revision of the PCB.

I won't argue that.
I am not going to defend them and the lack of delivery/communication etc, but I do know a lot about being on the receiving end of a lot of pressure from people to deliver something. And it is nly right to point out there can be a lot more to it than people are assuming.
« Last Edit: May 29, 2013, 09:56:28 pm by EEVblog »
 

Online Andy Watson

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Re: openvizsla......... still......
« Reply #20 on: May 29, 2013, 10:26:30 pm »
Ben and Phil have demonstrated that they are quite capable of ignoring any amount of screaming.  They could have published the design for peer review and still ignored the replies (there are only 580 backers, not thousands).

How can you know that? Just because they don't reply much? ...

Have a look at the comments section of their project page. It contains many, many requests begging for an update, or even simple confirmation that they are still on the planet.

Quote

Unless you have been in this position it's hard to understand.


I'll have to take your word on that.
Quote
[
Quote
I backed this project because it was billed as "open", it's in the title of the project!

Like I said, that does not have to extend to the design process.
If you think it does/should, then that's just your opinion and assumption.
Unless they specifically said they would share the info during the design process, then you can't just automatically assume they would do that.
And like I  said again, there can be good reason not share that info unless it's released or close to released. Many OSHW people do not release info until the project is finished.


This, from the homepage of the project " OpenVizsla will be a completely open design of a device ...", and "We will release schematics and design files under a Creative Commons license and we will set up a community to develop the device firmware, FPGA HDL, and client software."  Lacking any statement to the contrary I don't see it as an assumption to interpret  "completely open" as meaning, completely open.

 

Offline EEVblog

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Re: openvizsla......... still......
« Reply #21 on: May 29, 2013, 10:37:44 pm »
Have a look at the comments section of their project page. It contains many, many requests begging for an update, or even simple confirmation that they are still on the planet.

As I said, that is no indication what so ever that they would be "immune" to comment bombardment from an open design process as you claimed.

Quote
This, from the homepage of the project " OpenVizsla will be a completely open design of a device ...", and "We will release schematics and design files under a Creative Commons license and we will set up a community to develop the device firmware, FPGA HDL, and client software."  Lacking any statement to the contrary I don't see it as an assumption to interpret  "completely open" as meaning, completely open.

They made no statement at all saying they would open the hardware design process before the unit ships or they deem it to be ready to be released. The only thing it implies is that once it ships, the data has to be made available, or possibly once the hardware if finalised.
Once again, there are good reason not to release hardware info before the hardware is absolutely final.
What if they released the info as you wanted early and you spent ages working on the firmware or hacking it etc, only to find they changed the hardware again before release and all your work was for squat. You'd be a tad miffed, yeah? (also, replace "you" with "anyone else")
Sorry, but I think you may have simply assumed too much here.
« Last Edit: May 29, 2013, 10:42:52 pm by EEVblog »
 

Online Andy Watson

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Re: openvizsla......... still......
« Reply #22 on: May 30, 2013, 01:38:53 am »
As I said, that is no indication what so ever that they would be "immune" to comment bombardment from an open design process as you claimed.
I don't think I claimed that they would be immune to comment, only that they appear to be able to ignore the screaming, or more accurately, they appear to be able to ignore the multitude of very reasonable requests for information (any information). With the wisdom of hindsight it would perhaps have been a good thing if they weren't so "immune" to comment.

Quote
They made no statement at all saying they would open the hardware design process before the unit ships or they deem it to be ready to be released. The only thing it implies is that once it ships, the data has to be made available, or possibly once the hardware if finalised.
I think we'll have to differ on the interpretation of "completely open", especially when it's put in the context "community", "development" of an already "proven" design.

Quote
Once again, there are good reason not to release hardware info before the hardware is absolutely final.

Those reasons are usually to avoid giving intelligence to competing developers, but this is not a competition.  Or is it? With all the secrecy that surrounds this project it is becoming increasing difficult to not reach the conclusion that (as another backer put it) "something fishy is going on."
Quote
What if they released the info as you wanted early and you spent ages working on the firmware or hacking it etc, only to find they changed the hardware again before release and all your work was for squat. You'd be a tad miffed, yeah? (also, replace "you" with "anyone else")
It would be most unlikely that "all" the work was worth squat, you (I) would have probably learned a great deal along the way. In the worst case scenario you could revert to the earlier hardware design and go-it alone.  Yes I would be miffed. But that's a "what if" scenario. I am considerably more miffed at the reality. The reality is that promise after promise has amounted to squat. Offers of help have been rebuffed. The budget, and more, appears to have been used up (but again, there's no sound information available). Ben's last communiqué was decidedly downbeat with regard to finishing the project. So it looks like the reality is going to be diddly squat squared. In your what if scenario at least we would have some hardware to fall back to.
Quote
Sorry, but I think you may have simply assumed too much here.
I don't think it is too much too assume the we share a common language, at least with regard to "completely open".
 

Offline Corporate666

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Re: openvizsla......... still......
« Reply #23 on: May 30, 2013, 06:02:29 am »
I think the very vast majority of people would get in way over their head if they started a KS project.  I started doing product development about 13 years ago, and the first 2-3 projects I brought to market were over budget, behind schedule, lacked features I intended to include, and had design 'flaws' (or maybe bodges is a better word?) that I would have changed if I had more time and money.

13 years later, and I know how to do it now.  And I *still* run into occasional problems.  But I am always sure never to promise anything, never to give ETA's to people, never to get caught up in a series of exaggerations to quiet nagging customers, etc. 

I think the OpenVizsla guys are almost certainly well intentioned, but they have no idea at all about product design or about managing it from a business standpoint.  They are clearly way in over their heads, or at least, way in over what they thought they were getting into.  I feel bad for them and I can sympathize.

Now is the hardest part... they can either develop an adversarial/spiteful view of their backers (who in some cases probably deserve it), or they can work overtime to get the damn thing done and be done with it. 

More likely they will do the former - as is the want of most would-be-but-naive product developers.
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Online mikeselectricstuff

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Re: openvizsla......... still......
« Reply #24 on: May 30, 2013, 09:05:30 am »
"A man's got to know his limitations"....
I think the biggest mistake many people make is not to limit quantities of deliverable rewards to what they can conceivably handle - obviously it can take some experience to know what this might be, but allowing a $20K target to go to several hundred K is just silly.
You can always either extend after researching more if it gets popular, or just run another kickstarter later.
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Offline swSteve

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Re: openvizsla......... still......
« Reply #25 on: May 30, 2013, 02:36:56 pm »
I can see what you're talking about. But this project was sold as open.

An "open" project does not have to be open during the development process, only when complete. (unless they specifically promised otherwise?)
There can in fact be big downsides to going open during the design process, as I can well attest to with my PSU series. You end up with a thousand people screaming at you to do it this way, do it that way, asking questions and demanding things which start getting you off track etc.

Are you the guy that writes those lengthy software licenses with all the asterisks?

OK

We gave those guys more than 2 years which was more than fair and respectful.

cheers
Steve
 

Offline c4757p

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Re: openvizsla......... still......
« Reply #26 on: May 30, 2013, 02:42:56 pm »
I can see what you're talking about. But this project was sold as open.

An "open" project does not have to be open during the development process, only when complete. (unless they specifically promised otherwise?)
There can in fact be big downsides to going open during the design process, as I can well attest to with my PSU series. You end up with a thousand people screaming at you to do it this way, do it that way, asking questions and demanding things which start getting you off track etc.

Are you the guy that writes those lengthy software licenses with all the asterisks?

Expecting an "open" project to be open during development unless otherwise specified is like expecting that you can open a gift before you receive it, just because it's going to be yours at some point.
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Offline EEVblog

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Re: openvizsla......... still......
« Reply #27 on: May 30, 2013, 02:55:18 pm »
Are you the guy that writes those lengthy software licenses with all the asterisks?

No, I'm the guy that understands the practical reasons for things.

Quote
We gave those guys more than 2 years which was more than fair and respectful.

Sure, you'll get no argument for me.
They should have had the balls to admit long ago that the project was never going to get there, and at that point admit defeat and simply release/ship whatever they had.
 

Offline Smokey

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Re: openvizsla......... still......
« Reply #28 on: August 02, 2013, 05:42:13 am »
Happened to be looking at another kickstarter and figured I'd check in on OpenVizsla... Check this out...

http://www.kickstarter.com/projects/bushing/openvizsla-open-source-usb-protocol-analyzer/posts/522345

The plot thickens.....
 

Offline Bored@Work

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Re: openvizsla......... still......
« Reply #29 on: August 02, 2013, 06:10:28 am »
Happened to be looking at another kickstarter and figured I'd check in on OpenVizsla... Check this out...

http://www.kickstarter.com/projects/bushing/openvizsla-open-source-usb-protocol-analyzer/posts/522345

The plot thickens.....

Do you believe the story? Amazing.
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Offline Rasz

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Re: openvizsla......... still......
« Reply #30 on: August 02, 2013, 06:16:21 am »
cool story, except "Project by bushing", not "project by pytey". This guy is FKCD for the rest of his life now, he is "the guy that defrauder a bunch of people on kickstarter". Nobody cares he send money to some dude in Hungary.

ps: his latest pcb design could be substituted with $40 chinese fpga board + usb phy on separate board = $30000 in hardware. Instead he once again spins some random boards nobody will ever receive.
« Last Edit: August 02, 2013, 06:22:41 am by Rasz »
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Offline EEVblog

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Re: openvizsla......... still......
« Reply #31 on: August 02, 2013, 07:34:28 am »
http://www.kickstarter.com/projects/bushing/openvizsla-open-source-usb-protocol-analyzer/posts/522345
The plot thickens.....

Ok, I'll state the bleeding obvious.
If the project can be done with a spartan 6 FPGA and FTDI board and there is enough money left to manufacture them, why not do this:
1) Return the remaining money
2) Continue to do the HDL design based on a standard Spartan 6 FPGA platform (pick one of many) as a show of good faith and release to the wild.
Those who want to then make one can make one, those who don't at least have some money back.

IMO that's the only way to get any shred of credibility back.
 

Offline free_electron

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Re: openvizsla......... still......
« Reply #32 on: August 02, 2013, 07:54:10 am »
what i read in that post is : The current version boards and parts are in hungary, pilfered by some dude. To solve this problem we're going to make a totally new board, with new and totally different parts ... untested untried and then we will write the HDL. if the hdl doesn't work and we need more resources we will redo the board once again...

The 'run for the hills part' is the following:
Since they don't know what is needed and clearly state they may have to 'respin the hardware, depending on the HDL' this means 1 thing and one thing only : there is NO WORKING HDL (fpga code)!. If there were a completed HDL they would know what is required as far as supporting hardware goes.

So this project is just a blank board and some parts. It has never run , never booted and never captured even one USB packet. it's not even sure the selected fpga and memory is large enough / fast enough or adequate for the task at hand..

pigs flying , thick layers of ice in hell and chickens needing dentists .... something along those lines...

-edit-.. i just looked at the schematics. this thing cannot and will not work... here is why : they take an A side and a B side connector ,string em together and then splice the DP and DM into a 3340 transceiver. YOU CAN NOT DO THAT ! usb is point to point. you can not splice the bus ! you would need two USB transceiver cells. and have the data flow through the FPGA.

Furthermore, the 3340 is only a FULL SPEED transceiver ( USB 1.0 ) . it cannot handle 2.0. for 2.0 it has a built in multiplexer that disconnects itself from the bus and allows an external PHY to take over.

so this thing isn't even 2.0 capable !
« Last Edit: August 02, 2013, 08:11:07 am by free_electron »
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Offline Bored@Work

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Re: openvizsla......... still......
« Reply #33 on: August 02, 2013, 08:38:48 am »
what i read in that post is : The current version boards and parts are in hungary,

And the parts are so special, one can't get them in the US of A. Made from some secret Hungarian paprika sauce ... It is the "blame the bloody foreigner" excuse.

Quote
Furthermore, the 3340 is only a FULL SPEED transceiver ( USB 1.0 ) . it cannot handle 2.0. for 2.0 it has a built in multiplexer that disconnects itself from the bus and allows an external PHY to take over.

This is where the secret Hungarian paprika sauce was coming in ...
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Offline Baliszoft

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Re: openvizsla......... still......
« Reply #34 on: August 02, 2013, 08:58:23 am »
I feel ashamed being a hungarian. and this is not the first time lately
 

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Re: openvizsla......... still......
« Reply #35 on: August 02, 2013, 09:12:23 am »
-edit-.. i just looked at the schematics. this thing cannot and will not work... here is why : they take an A side and a B side connector ,string em together and then splice the DP and DM into a 3340 transceiver. YOU CAN NOT DO THAT ! usb is point to point. you can not splice the bus ! you would need two USB transceiver cells. and have the data flow through the FPGA.
Agreed. Signal integrity and termination will be terrible, and probably also negotiation.

Furthermore, the 3340 is only a FULL SPEED transceiver ( USB 1.0 ) . it cannot handle 2.0. for 2.0 it has a built in multiplexer that disconnects itself from the bus and allows an external PHY to take over.
The datasheet for the 3343 suggests otherwise. Or did I miss a footnote somewhere?
 

Offline firewalker

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Re: openvizsla......... still......
« Reply #36 on: August 02, 2013, 09:26:57 am »
I feel ashamed being a hungarian. and this is not the first time lately

Why?

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Offline free_electron

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Re: openvizsla......... still......
« Reply #37 on: August 02, 2013, 10:07:11 am »

Agreed. Signal integrity and termination will be terrible, and probably also negotiation.


That's not it .. There is no menage-a-trois on usb , USB is point to point ! you can not have a third transceiver cell on the pair of wires. even if that transceiver would be listen only. You need to have two transceivers and basically replicate the dataflow. that means all data has to go through the fpga.

you can't simply splice the wires ...

@alm : they are using a 3340 not a 3343 ... look at the block diagram. they clearly show the switch to bring out the DP and DM to wire up to a high speed phy. the internal phy is full speed only.
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Offline krivx

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Re: openvizsla......... still......
« Reply #38 on: August 02, 2013, 10:16:24 am »
@alm : they are using a 3340 not a 3343 ... look at the block diagram. they clearly show the switch to bring out the DP and DM to wire up to a high speed phy. the internal phy is full speed only.

Looks like they switched to a 3343 a month ago, check the list of commits on their github https://github.com/openvizsla/ov_ftdi/tree/master/hardware
 

Offline FrankBuss

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Re: openvizsla......... still......
« Reply #39 on: August 02, 2013, 10:20:36 am »
That's not it .. There is no menage-a-trois on usb , USB is point to point ! you can not have a third transceiver cell on the pair of wires. even if that transceiver would be listen only. You need to have two transceivers and basically replicate the dataflow. that means all data has to go through the fpga.
You don't need two transceivers, you could sample the bus. There are differential probes with 1 pF / 1 MOhm: http://www.tek.com/differential-probe I guess would be much less expensive on the board and if you just want to check if it is 1 or 0, and not measuring the eye-diagram etc. But could be tricky for 480 Mbit/s high-speed USB, and the clock regeneration would be hard. Maybe a differential amplifier to decouple it from the USB bus, and then a transceiver chip, if it can work in receive mode, only.
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Offline Short Circuit

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Re: openvizsla......... still......
« Reply #40 on: August 02, 2013, 10:40:34 am »

Agreed. Signal integrity and termination will be terrible, and probably also negotiation.


That's not it .. There is no menage-a-trois on usb , USB is point to point ! you can not have a third transceiver cell on the pair of wires. even if that transceiver would be listen only. You need to have two transceivers and basically replicate the dataflow. that means all data has to go through the fpga.

you can't simply splice the wires ...

Need maybe, but that is not how things are done in commercial USB analyzers.

Here's a couple of pics inside an Ellisys USB1.1 analyzer;
(uses Cypress CY7C68013, Xilinx Spartan XC2S50 and an ISP1107 transceiver)

And a warning from the LeCroy (former CATC) UsbMobile manual:
Quote
USBMobile T2 (and USBMobile HS) USB is not a hub device. It connects to a USB
branch by inserting a non-intrusive, high-impedance tap. Because poor signal quality in
the middle of a USB cable, LeCroy recommends using the shortest possible cables, so
that total length of both cables together is less than six feet. The USB cables provided
with your Analyzer meet this requirement. When longer cables are used, the Analyzer
might record incorrect data.
 

Offline marshallh

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Re: openvizsla......... still......
« Reply #41 on: August 02, 2013, 01:14:46 pm »
I have a Usb 3.0 analyzer, it's done via passive tapping as well, though it is quite elaborate and expensive. The signal is redriven right after the passive taps to the DUT. (Reconstructed via active redriver, not just amplified) So the net effect on the signal is nil.
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Re: openvizsla......... still......
« Reply #42 on: August 02, 2013, 02:40:05 pm »
I feel ashamed being a hungarian. and this is not the first time lately

If that wasn't clear, in my opinion I think it is just a lame excuse to blame it on the Hungarian guy and make him the scapegoat. He might have parts, he might have boards, but it is very unlikely that one can get these alleged very special parts in Hungary only.

The hole reason given by this bushing guy why he needed to do yet another design and board sounds like bullshit to me.
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Offline free_electron

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Re: openvizsla......... still......
« Reply #43 on: August 02, 2013, 04:54:06 pm »
I am writing my finding ps based o their latest published schematics. That shows a 3340, not a 3343.

Yes you can passively tap a usb signal. Agilent scopes can sniff usb using two simple passive probes.
Yes you can also use an active amolifier or even a barebones transceiver cell like a philips isp1107.
But you cant do it with that 334x as that thing has logic on board. When it sees a usb packet it will (may) react to it. The isp1107 is a dumb isb compliant differntial driver and differential receiver. You can flick that in receive only mode and bobs your uncle. Note that the isp1107 is full speed only (1.1 : 12 megabit) it cant do high speed 480 megabit 2.0) But, if you want to sniff the high speed usb2.0 (which is 480MHz ) you will need an fpga with a bit more oomph...

This project is a complete fail. They have no clue what hardware they really need, are simply slapping some parts on a board, then will try to write some hdl , very quickly finding out their fpga is too small too slow, the usb phy is incorrect and there is no chance inhell it will do 2.0 .. And then what ' oh we're going to spin the board once more like we said... Burning some more money...

It's dead. Bury it.
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Offline Baliszoft

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Re: openvizsla......... still......
« Reply #44 on: August 02, 2013, 04:56:03 pm »
I feel ashamed being a hungarian. and this is not the first time lately

If that wasn't clear, in my opinion I think it is just a lame excuse to blame it on the Hungarian guy and make him the scapegoat. He might have parts, he might have boards, but it is very unlikely that one can get these alleged very special parts in Hungary only.

The hole reason given by this bushing guy why he needed to do yet another design and board sounds like bullshit to me.

They already failed with this project IMHO, and should return the money to the backers. And i guess they wont be able to do that.
 

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Re: openvizsla......... still......
« Reply #45 on: August 02, 2013, 05:54:29 pm »
They already failed with this project IMHO, and should return the money to the backers. And i guess they wont be able to do that.

He admits there is enough money left to do a new run of boards, so there is absolutely no reason why backers can't be refunded at least in part.
 

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Re: openvizsla......... still......
« Reply #46 on: August 02, 2013, 06:52:40 pm »

Agreed. Signal integrity and termination will be terrible, and probably also negotiation.


That's not it .. There is no menage-a-trois on usb , USB is point to point ! you can not have a third transceiver cell on the pair of wires. even if that transceiver would be listen only. You need to have two transceivers and basically replicate the dataflow. that means all data has to go through the fpga.

you can't simply splice the wires ...

@alm : they are using a 3340 not a 3343 ... look at the block diagram. they clearly show the switch to bring out the DP and DM to wire up to a high speed phy. the internal phy is full speed only.
I'm not familiar with  details of USB transceivers, but surely by limiting cable length to, say 1m, you can make use of the margin between the 5m cable limit and the 1m cable used to allow a passive montoring probe with non-trivial loading.

I'd have thought perhaps a better way to do this is for the monitor to pretend to be a hub, that way you avoid any loading issues.
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Offline Short Circuit

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Re: openvizsla......... still......
« Reply #47 on: August 02, 2013, 09:04:04 pm »

I'd have thought perhaps a better way to do this is for the monitor to pretend to be a hub, that way you avoid any loading issues.

That is the last thing you want from an USB analyzer because a hub is an active device at protocol level also. So it screws with timings and with the enumeration process. That is not a problem with a perfect device and a perfect host running flawless drivers, but that is not what we need USB analyzers for  ^-^

For example Last time I had to dive into low-level USB debugging, the problem appeared when the device was connected to a hub, went away when connected directly to host...
 

Offline firewalker

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Re: openvizsla......... still......
« Reply #48 on: August 02, 2013, 09:06:55 pm »
Apart from the sniffing /taping and the way to "wrap" the usb.

The analyzer part? What will the offer? Raw data?

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Re: openvizsla......... still......
« Reply #49 on: August 02, 2013, 09:09:20 pm »

They already failed with this project IMHO, and should return the money to the backers. And i guess they wont be able to do that.

And why should they return the money? Read the kickstarter terms - if you back something on kickstarter - YOU risk losing your money without getting anything in return. That is the clear and stated terms.

So Kickstarter is a "gambling site" - so never put in more than you can afford to loose. If it was risk free - it would not be a Kickstarter to help people lift products ' off the ground '

Less than 1 in 10 projects founded by professional investors actually turn into profitable companies. But it does seem like more than 1 in 10 projects in kickstarter turns something out to their "investors"
 

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Re: openvizsla......... still......
« Reply #50 on: August 02, 2013, 10:10:49 pm »

I'd have thought perhaps a better way to do this is for the monitor to pretend to be a hub, that way you avoid any loading issues.

That is the last thing you want from an USB analyzer because a hub is an active device at protocol level also. So it screws with timings and with the enumeration process. That is not a problem with a perfect device and a perfect host running flawless drivers, but that is not what we need USB analyzers for  ^-^

For example Last time I had to dive into low-level USB debugging, the problem appeared when the device was connected to a hub, went away when connected directly to host...
True, but I suspect the vast majority of potential users are more interested in reverse engineering and developing device firmware, so may be  a route worth exploring for a low-cost product aimed at these applications. 
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Re: openvizsla......... still......
« Reply #51 on: August 02, 2013, 10:17:42 pm »
And why should they return the money?

Because your name become shit, and maybe just because it's the right thing to do?

Quote
Read the kickstarter terms - if you back something on kickstarter - YOU risk losing your money without getting anything in return. That is the clear and stated terms.

There is more to life, projects, promises and the social condition than terms and condition on some stupid website you happen to use.

Quote
Less than 1 in 10 projects founded by professional investors actually turn into profitable companies. But it does seem like more than 1 in 10 projects in kickstarter turns something out to their "investors"

It's not really the same game. Although a lot of people will pretend it is to explain away failures and a lack of morals.
 

Online kaz911

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Re: openvizsla......... still......
« Reply #52 on: August 02, 2013, 11:32:49 pm »
And why should they return the money?

Because your name become shit, and maybe just because it's the right thing to do?

Quote
Read the kickstarter terms - if you back something on kickstarter - YOU risk losing your money without getting anything in return. That is the clear and stated terms.

There is more to life, projects, promises and the social condition than terms and condition on some stupid website you happen to use.

Quote
Less than 1 in 10 projects founded by professional investors actually turn into profitable companies. But it does seem like more than 1 in 10 projects in kickstarter turns something out to their "investors"

It's not really the same game. Although a lot of people will pretend it is to explain away failures and a lack of morals.

We can all agree what the ETHICAL thing to do is - and that is what you and I would try to do.

But once you put your money into IGG or Kickstarter projects - expect ZERO - and be pleasantly surprised IF and WHEN you get your PERK. You do not have the right to anything more. The PERK is not a promise - it is a "If we succeed you might get XXX as an appreciation for your donation" - but many people takes it as a "product purchase" which it is NOT. It is a pure donation.
 

Offline free_electron

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Re: openvizsla......... still......
« Reply #53 on: August 02, 2013, 11:42:52 pm »
Kickstarter is basically a site that deals with 3 words : fool , easily , parted . You provide the money.
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Offline FrankBuss

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Re: openvizsla......... still......
« Reply #54 on: August 02, 2013, 11:59:07 pm »
But once you put your money into IGG or Kickstarter projects - expect ZERO - and be pleasantly surprised IF and WHEN you get your PERK. You do not have the right to anything more. The PERK is not a promise - it is a "If we succeed you might get XXX as an appreciation for your donation" - but many people takes it as a "product purchase" which it is NOT. It is a pure donation.
In general you are right. But they wrote "We have been working on this project in various forms for over two years now, and large parts of the hardware design have already been proven." in the project description. This was in 2010. So the naïve reader would expect that they had already some working hardware and successfully sniffed some USB packets. It is a bit surprising that they change major parts of the hardware all the time and maybe even don't have any working HDL code for the FPGA (see their Github repository: https://github.com/openvizsla/ov_ftdi ).

It's ok, if you were honest from the beginning, saying this is a hobby project, we have no clue about FPGA high speed hardware design and no working prototypes, and we can't promise that we can do it. But if you lied, you have to admit it and at least pay back the money.
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Offline EEVblog

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Re: openvizsla......... still......
« Reply #55 on: August 03, 2013, 12:22:11 am »
It's ok, if you were honest from the beginning, saying this is a hobby project, we have no clue about FPGA high speed hardware design and no working prototypes, and we can't promise that we can do it. But if you lied, you have to admit it and at least pay back the money.

And that's the kicker. Screw the KS terms and conditions, they are irrelevant from a moral/ethical standpoint.
If you lie (i.e. commit fraud) and don't deliver then you are obligated to give the money back.
If you promise something then you are obligated to deliver, or give the money back.

And by obligated I of course mean by conscience & your reputation.
You may not be legally obligated to do so (it takes a judge to determine that for such individual cases), but that varies greatly from one local law to another. Basically, the KS terms and conditions will mean very little or squat in a court of law I suspect. Consumer protection and other common law have fairly wide scope that trumps most other agreements.
And in most countries, obtaining money by deliberate deceit is fraud, and nothing will save you there. All it takes is one backer who is pissed off enough to take you on.

The backers of these crowd funded campaigns will ultimately determine what is right and wrong, and so far it seems many people have been quite weak and think that the KS or Indiegogo terms and conditions mean something and they have done their money. They only mean something if you let it. People going around pointing out the KS terms and conditions and have the creator is not obligated to deliver anything are not helping, and ultimately it will be self fulfilling prophecy.
 

Online kaz911

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Re: openvizsla......... still......
« Reply #56 on: August 03, 2013, 01:01:10 am »
Both Kickstarter and IGG requires you to deliver the perks. But they take no responsibility - and leaves all problem resolution to be between creators and the "purchaser". Which in my mind turns any payment into a donation.

Anyway - I would like to see future "crowd funding" systems where money could be handed over in tranches based on partial goals met.
 

Offline Rasz

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Re: openvizsla......... still......
« Reply #57 on: August 03, 2013, 08:01:14 am »
Kickstarter is basically a site that deals with 3 words : fool , easily , parted . You provide the money.

So you agree with us that projects that fail like this ones are basically SCAMS and person running them is a scammer and a fraudster (unless he returns money)
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Offline FrankBuss

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Re: openvizsla......... still......
« Reply #58 on: August 03, 2013, 08:57:50 am »
I don't think that they are fraudsters, because I guess they didn't intent to screw it up so badly and maybe they can still build something. At least full-speed USB should be possible with the hardware, if they figure out how to configure the receiver that it doesn't interfere with the signal. At USB full-speed the FPGA can run circles around the signal and even clock recovery with digital algorithms should be possible, if they feed the differential signal with a buffer directly to the FPGA.

That said, the conclusion might be that you should not fund a project with a cute dog video, only :) , but without demonstrating a working proof of concept.
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Re: openvizsla......... still......
« Reply #59 on: August 03, 2013, 09:15:24 am »
Even if they could build a USB full-speed analyzer, what's the point? How many people are designing/hacking USB full-speed equipment these days? You should be able to probe USB full-speed with a decent logic analyzer with USB decoding. USB 2 high-speed is the bare minimum to be useful in my opinion.
 

Offline free_electron

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Re: openvizsla......... still......
« Reply #60 on: August 03, 2013, 09:49:12 am »
Kickstarter is basically a site that deals with 3 words : fool , easily , parted . You provide the money.

So you agree with us that projects that fail like this ones are basically SCAMS and person running them is a scammer and a fraudster (unless he returns money)
Not necessarily.  they may started this with good intent , bitten off far more than they can chew and took a bit of a 'lets wing it and see what happens'...

today they still have no HDL .. their schematics are just a generic fpga with dram and a usb phy (unfit for purpose) bolted on and an FTDi interface chip.
that schematic can be whipped up in less than a day by anyone who knows a coupe of things about FGPa. it doesn't take a genius to come up with that one. some appnotes , some symbols. place and route... give it another two days to draw the board.

the genius part is needed to code the HDL ( the FPGA code) . and that is  a totally different can of worms ...
I wouldn't dare tackle that one. designing the hardware and the pcb ? yep . gimme. i'll cook it up. that sniffer core and the pc software ? that's endless misery ... I already have enough work.

and that is where this project is failing / will fail. recording 1 and zero is only one aspect. building a packet representer is another...
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Offline FrankBuss

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Re: openvizsla......... still......
« Reply #61 on: August 03, 2013, 09:51:15 am »
Even if they could build a USB full-speed analyzer, what's the point? How many people are designing/hacking USB full-speed equipment these days? You should be able to probe USB full-speed with a decent logic analyzer with USB decoding. USB 2 high-speed is the bare minimum to be useful in my opinion.
A good full-speed analyzer costs still more than their device: http://www.totalphase.com/products/beagle_usb12/ so people would get something for their money, if they write some nice host-side software for it. And many devices, like joysticks and other HID devices, modems etc., are just low-speed or full-speed. And full-speed is still used for many new embedded systems developments, because cheap microcontrollers don't have high-speed USB and it is not necessary for e.g. a firmware update or configuration over USB. But right, looks like the Kinect or the iPhone sync which they mention on the project page are high-speed.
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Offline marcan

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Re: openvizsla......... still......
« Reply #62 on: August 06, 2013, 05:18:49 am »
Dave, I don't get why you feel that returning the remaining money is the only option now. If bushing can manufacture the design (a USB 2.0 analyzer) with the remaining funds and ship it out to backers with the remaining funds, then what's the harm done? I don't see how, at this stage, returning the available funds (meaning backers get back x% of what they paid and get nothing) is better than shipping them working analyzers (meaning backers get what they paid for, albeit much later than expected). I also don't see how you expect people to be able to build them for cheaper (if the funds are just barely sufficient to manufacture the design in the quantity of the kickstarter, they aren't going to be sufficient for everyone to run off and make their own in single quantities). You still need the sniffer frontend part (USB ports and a PHY wired properly to minimize the impact of the PHY on the link), which isn't something you can just buy off the shelf.

FWIW, the USB3340 is a high-speed PHY, and so is the 3343 (I have no clue where the idea that the 3340 is FS-only came from). Passive tapping via a PHY like this is used in the Beagle USB 480, which is a proven commercial USB analyzer (using the same damn PHY chip family!):
http://www.flickr.com/photos/eric_agan/6994240004/#

Except TotalPhase charge $1.4k for their version.

That PHY has configurable termination, which means it can be put into a mode where it has high-z termination but receives data, which makes it work fine for sniffing. It also supports full/low-speed mode.. I don't know why the Beagle has a separate LS/FS PHY - maybe because the 334x datasheet claims it can't support operation as an upstream FS hub port (it can't decode the mixed FS/LS signaling there, although it can do the host side), so that might preclude using OV as a USB sniffer on an FS hub's upstream port... but that's a very niche use case. Even then, the 334x has a passthrough mode where it only does the differential tx/rx part and passes through raw FS/LS bits to the FPGA, so if you implement your own SERDES for FS you might be able to work around that even.
« Last Edit: August 06, 2013, 05:22:33 am by marcan »
 

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Re: openvizsla......... still......
« Reply #63 on: August 06, 2013, 08:02:17 am »
Dave, I don't get why you feel that returning the remaining money is the only option now.

Because it has turned into a complete farce.

Quote
If bushing can manufacture the design (a USB 2.0 analyzer) with the remaining funds and ship it out to backers with the remaining funds, then what's the harm done?

IF???
So far he has not demonstrated that he can't delivery anything after how many years?
Now you think he can deliver starting from scratch again? Come on, get real.

Quote
I don't see how, at this stage, returning the available funds (meaning backers get back x% of what they paid and get nothing) is better than shipping them working analyzers (meaning backers get what they paid for, albeit much later than expected).

Sure, but the kicker is that it's highly unlikely given his past performance (or lack of it) that he will deliver anything at all.
A working analyser won't just magically appear. It requires a lot of time, effort, and expertise. He probably has the expertise to get it done, but he has clearly shown he doesn't not have the ability (for whatever reason) to put in the effort.
 

Offline EEVblog

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Re: openvizsla......... still......
« Reply #64 on: August 06, 2013, 08:08:27 am »
Anyway - I would like to see future "crowd funding" systems where money could be handed over in tranches based on partial goals met.

That would be great, but then completely puts the onus on crowd funding site to vet and "approve" that task is done. That is time consuming and open them up to liability.
Of course, you could crowd source that part too. Have a "thumbs up" from users that the creator has reached the goal. Get say 90% thumbs up and the next round of funding is charged.
 

Offline FrankBuss

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Re: openvizsla......... still......
« Reply #65 on: August 06, 2013, 08:29:54 am »
http://www.freelancer.com has such a milestone system, and they handle disputes, if a freelancer and a buyer don't agree. I've used it as a freelancer, just for testing it for smaller programming projects, but I couldn't live on it, because I can't compete with low-wage countries. And I've used it as a buyer, where the results were very variable, depending on the freelancer. Sometimes you get what you want, sometimes you need the dispute system, but they do a good job.

Now enhance it to multiple buyers and you are done. The website has a developer API, so should be possible to integrate it in your own multi-buyer crowdfunding system.
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Online kaz911

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Re: openvizsla......... still......
« Reply #66 on: August 06, 2013, 01:34:55 pm »
Anyway - I would like to see future "crowd funding" systems where money could be handed over in tranches based on partial goals met.

That would be great, but then completely puts the onus on crowd funding site to vet and "approve" that task is done. That is time consuming and open them up to liability.
Of course, you could crowd source that part too. Have a "thumbs up" from users that the creator has reached the goal. Get say 90% thumbs up and the next round of funding is charged.

I actually think the Crowd Funding sites would like it :) that meant they could keep the money for longer and earn some interest :) But yes - a thumbs up thing would be great - in some balanced form as there will always be people who will pressure for "more" to release the money. So maybe both a thumbs up and thumbs down. That also eliminates the "couch potato" voters who does not get their finger out of their "b*t" to vote either way.
 

Offline marcan

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Re: openvizsla......... still......
« Reply #67 on: August 06, 2013, 09:06:47 pm »
IF???
So far he has not demonstrated that he can't delivery anything after how many years?
Now you think he can deliver starting from scratch again? Come on, get real.
I've seen the BOMs, with cost, and I have a prototype coming my way (I signed up to help with the HDL... wish me luck), so yes, I think he (barely) can. Probably putting in (more) of his personal money, but he's the kind of person who would much rather do that and get this over with than disappear and do everyone wrong.

Sure, but the kicker is that it's highly unlikely given his past performance (or lack of it) that he will deliver anything at all.
A working analyser won't just magically appear. It requires a lot of time, effort, and expertise. He probably has the expertise to get it done, but he has clearly shown he doesn't not have the ability (for whatever reason) to put in the effort.
I know this project when viewed as a whole is ridiculous at this stage, but the story that he tells about pytey going MIA is true. For the past two years most of the time OV was blocked waiting for pytey to sort out manufacturing issues in Hungary. I'd like to point out that ever since the "Ripping the band-aid off" update (i.e. when bushing wrote off pytey's side of the deal and started driving the project entirely by himself), the entire design process has been open and anyone can watch on GitHub, where there has been a steady stream of commits. Just one month after the restart he has prototypes on hand which are getting shipped to volunteers who will be helping with the firmware. Yes, it's two freaking years and a half too late, but you can't deny that progress is actually being made at a reasonable pace now, no?
 

Offline EEVblog

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Re: openvizsla......... still......
« Reply #68 on: August 06, 2013, 09:43:07 pm »
Yes, it's two freaking years and a half too late, but you can't deny that progress is actually being made at a reasonable pace now, no?

I don't know, I haven't looked, I'll take your word for it.
 

Offline marcan

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Re: openvizsla......... still......
« Reply #69 on: September 13, 2013, 08:48:42 pm »
Just thought I'd post this update. First USB data acquired and sent back to the host:
http://www.kickstarter.com/projects/bushing/openvizsla-open-source-usb-protocol-analyzer/posts/597816

We've also verified the SDRAM (@100MHz, probably more with HDL tweaks but 100MHz is plenty already). FPGA sizing looks good too; in fact we might be able to downgrade one notch and still fit it in. The next interesting bit to validate is that we can follow USB negotiation / the high-speed chirp in real time. The final architecture of the logic is also taking shape (re: buffering, filtering, etc.) although there are still many details to finalize.

(By the way, migen is awesome. If you know Python and you design RTL logic, you should try it.)
« Last Edit: September 13, 2013, 08:51:16 pm by marcan »
 

Offline free_electron

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Re: openvizsla......... still......
« Reply #70 on: September 13, 2013, 11:06:54 pm »
Good work !
Now, after the psoitive note : how long till we see the user interface like the CATC has ? With the nice packet drawings, decoding and all the other stuff.

A command line showing some hex data is so 18th century ...
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Offline mrflibble

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Re: openvizsla......... still......
« Reply #71 on: September 13, 2013, 11:27:53 pm »
how long till we see the user interface like the CATC has ? With the nice packet drawings, decoding and all the other stuff.

If they have even half a brain they use libpcap. Hell, feeding the bitstream to wireshark just might be a wee bit faster than cooking up something new and failing due to Out Of Time Error.
 

Offline mrflibble

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Re: openvizsla......... still......
« Reply #72 on: September 13, 2013, 11:31:38 pm »
(By the way, migen is awesome. If you know Python and you design RTL logic, you should try it.)

Well, I tried it. Tried to find an excuse to use it that is. Read the tutorial + user guide, but why would you want to use this, even if you do like auto-generated verilog?

I am all for new tools in the toolbox, but I didn't get an a-hah! moment when reading the docs... So maybe you spotted a nice usecase that I missed?
 

Offline marcan

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Re: openvizsla......... still......
« Reply #73 on: September 14, 2013, 09:29:33 am »
Re: UI, I think realistically speaking the #1 priority is getting the hardware to do everything it needs to do, and then ship the devices to backers. I'm sure the software side will benefit from having more people willing to chip in with some help. But yes, munging the output into pcap format to feed it to wireshark is one of the more logical approaches.

(By the way, migen is awesome. If you know Python and you design RTL logic, you should try it.)

Well, I tried it. Tried to find an excuse to use it that is. Read the tutorial + user guide, but why would you want to use this, even if you do like auto-generated verilog?

I am all for new tools in the toolbox, but I didn't get an a-hah! moment when reading the docs... So maybe you spotted a nice usecase that I missed?

It's a bit hard to explain. For one, the metaprogramming is *awesome*. One of the things that bugs me most about verilog is how tedious it is to build high-level structures (things like generate statements and for loops are... rather limited). With migen, you can just use bog-standard Python to make a generator for as complex a design as you want. There are built-in classes to generate things like FSMs, buses (of various kinds and features), FIFOs (async and sync), register banks, etc. Migen also makes clock domain handling easier by encapsulating them into a class that synchronous statements interact with, and it also takes care of reset handling (e.g. you can switch a design from an explicit reset to an implicit FPGA config-time reset by changing one line of code, instead of having to change every always block and register initializer to take out the reset signal).

The other nice thing is that migen draws a hard distinction between the logic (what actually makes it into the device), which is conceptualized as synchronous and combinatorial statementss, and the Python that is really just a metaprogramming language around it. It's a lot closer to the way we think when writing digital logic (i.e. the "registers with clouds of combinatorial logic between them" idea), and it makes it much harder to write code that won't synthesize. I wrote the SDRAM core without a testbench at first, and I had made a single off-by-one-cycle timing mistake - it just worked after I fixed that. That just never happens with Verilog. I also like Python's class model better than Verilog's module model (with migen your entire design becomes one huge Verilog module, and it knows how to rename things so they don't collide within it - so you can freely name things in Python as you see fit).

And, of course, the way mibuild wraps the Xilinx tools and makes it possible to build designs without dealing with the ISE mess directly is great. Its way of defining UCF files is also more compact.
 

Offline mrflibble

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Re: openvizsla......... still......
« Reply #74 on: September 14, 2013, 08:06:50 pm »
Okay, that sounds moderately interesting. :) As in, it sounds pretty damn neat! but that is then derated based on past experiences with other "sounds pretty damn neat" things just like it.

How is it in handling say 50% code written in pure verilog, and 50% code handled by migen? Ditto for mixed verilog + vhdl. Because ideally you'd want to be able to mix & match. Say you want to use a PLL core from coregen, plus have some old already proven modules.

Quote
I also like Python's class model better than Verilog's module model

Heh, that is easily done!  ;D verilog is total shit in that regard. So "total shit" vs "not my favorite but acceptable" ... yeah, python wins.

Mmmh, might be interesting to just give it a try. Any good examples to be found besides the stuff provided with the download? As in, any magic places on the internet to find extra resources for it? Because that might be one other issue with using it, tiny userbase.

PS: Ahem, just realized ... sorry for the off-topic.
« Last Edit: September 14, 2013, 08:31:19 pm by mrflibble »
 

Offline mrflibble

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Re: openvizsla......... still......
« Reply #75 on: September 14, 2013, 08:30:20 pm »
Oh yeah, do you happen to know if you can do the following in a non-painful way:

Generate an array of modules, and then generate constraints for those as well. Generate constraints, purely based on source file I mean. Mostly LOC's, but sometimes moderately creative ROUTE constraints as well. I have a solution for that, but sometimes it's not very pretty (nor maintainable).

In that regard VHDL is a bit nicer, since there you CAN write attributes during synthesis. In verilog if you want it on source level you can only use comment style. And comment style ... you cannot dynamically emit new comments that get parsed during synthesis.  :-\ So if you want the full feature set you end up using a (perl) script to update an external UCF file. And then comment the hell out of your source file so you still know what you're doing here.

And just to be clear, in all the above I mean verilog-2001. Not SystemVerilog or even verilog-2005. Since verilog-2001 is basically what you have to deal with if you use ISE.
 

Offline marcan

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Re: openvizsla......... still......
« Reply #76 on: September 15, 2013, 10:09:09 am »
How is it in handling say 50% code written in pure verilog, and 50% code handled by migen? Ditto for mixed verilog + vhdl. Because ideally you'd want to be able to mix & match. Say you want to use a PLL core from coregen, plus have some old already proven modules.
You can instantiate arbitrary Verilog modules (and VHDL too I think) easily. I almost did that with an external .v for our PLL, but I ended up instantiating the primitive straight from migen (here).

Mmmh, might be interesting to just give it a try. Any good examples to be found besides the stuff provided with the download? As in, any magic places on the internet to find extra resources for it? Because that might be one other issue with using it, tiny userbase.
Well, yeah, the documentation is... not comprehensive and somewhat outdated. I definitely wouldn't suggest it if you can't deal with that :). But I'm happy to work things out myself considering the good parts of migen that I've seen so far. Anyway, reasonable examples are probably our stuff and the canonical project that migen was developed for, milkymist-ng. I hope it matures a bit and becomes better documented with time.

Generate an array of modules, and then generate constraints for those as well. Generate constraints, purely based on source file I mean. Mostly LOC's, but sometimes moderately creative ROUTE constraints as well. I have a solution for that, but sometimes it's not very pretty (nor maintainable).
I'm not sure if there's a built-in way to fire off constraints to the UCF file from a module, but it should be trivial to implement yourself; just keep an array of modules that need constraints and then read it off in the platform's do_finalize method to generate the UCF. You could even use the module walking stuff in migen to make it automagic (e.g. for every module instance in use, check for a magic property/method and generate UCF from that).

I do some trivial UCF generation (clock period constraints) in ov3 here.

The beauty is that since it's python, it's really hard to come up with something that you *can't* do (migen may or may not do it off the shelf, but you can always implement it yourself in whatever way you deem reasonable).
« Last Edit: September 15, 2013, 10:14:30 am by marcan »
 

Offline MacAttak

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Re: openvizsla......... still......
« Reply #77 on: September 15, 2013, 10:39:37 am »
This side discussion is really interesting, but would probably be better if it was relocated to the FPGA section. Most people wouldn't think to click on an overdue crowdfunded project to find migen discussion :)
 

Offline mrflibble

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Re: openvizsla......... still......
« Reply #78 on: September 15, 2013, 12:03:01 pm »
Yeah, sorry about the off topic bits. I'll ask if an admin can move it. Maybe to the Open-source software for Verilog synthesis thread, since migen is precisely that.

Update: okay, request sent...
« Last Edit: September 15, 2013, 12:07:08 pm by mrflibble »
 

Offline marcan

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Re: openvizsla......... still......
« Reply #79 on: September 16, 2013, 11:54:22 pm »
Yeah, sorry about the off topic bits. I'll ask if an admin can move it. Maybe to the Open-source software for Verilog synthesis thread, since migen is precisely that.

Update: okay, request sent...

Not quite - migen generates Verilog, so it doesn't synthesize anything. It's a higher-level tool. But yes, this discussion should be moved elsewhere...
 

Offline desowin

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Re: openvizsla......... still......
« Reply #80 on: June 06, 2014, 10:33:52 pm »
Archeology time!  ;D

I have received OpenVizsla PCB. Now I need to order components and get it soldered.  Too bad mouser doesn't have the main FPGA (XC6SLX9-3TQG144C) available :( (I don't think > 49 USD for shipping from DigiKey is good deal...) so I'll have to order most parts from Mouser and the FPGA from some other (local) retailer.
 

Offline firewalker

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Re: openvizsla......... still......
« Reply #81 on: June 06, 2014, 10:43:21 pm »
You had pledged for a bare bone PCB?

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Offline mrflibble

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Re: openvizsla......... still......
« Reply #82 on: June 06, 2014, 10:48:44 pm »
Or you could just order everything from digikey, and pad the order to amount required for free shipping with fun dev-kits and those-passives-you always-run-out-of.
 

Offline krivx

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Re: openvizsla......... still......
« Reply #83 on: June 06, 2014, 11:14:11 pm »
Are they shipping orders or did you have a PCB fabbed? I don't know how to follow this project anymore. There hasn't been activity on github in a couple of months.
 

Offline desowin

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Re: openvizsla......... still......
« Reply #84 on: June 07, 2014, 11:58:54 pm »
You had pledged for a bare bone PCB?

Yes.

Are they shipping orders or did you have a PCB fabbed? I don't know how to follow this project anymore. There hasn't been activity on github in a couple of months.

I am 50 USD backer and received the reward (bare bone PCB and 50 USD off coupon code for fully assembled unit). There is some limited activity on the OpenVizsla backers mailing list. AFAIK the higher tier pledges will be sent later (fully assembled units) and after that the DIY kits (PCB + all components) will be sent (from the leftover parts after assembly).
 

Offline FrankT

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Re: openvizsla......... still......
« Reply #85 on: August 11, 2014, 04:48:20 pm »
Woot!  Mine arrived today.

Just need to find time to play with it now.
 

Offline firewalker

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Re: openvizsla......... still......
« Reply #86 on: August 11, 2014, 05:48:24 pm »
Lots of logos! :P

Test it and tell us if it is what it should be.

Alexander.
Become a realist, stay a dreamer.

 

Offline John_ITIC

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Re: openvizsla......... still......
« Reply #87 on: August 15, 2014, 04:48:35 pm »
I've been through the same thing Bushing and his team went through since, I too, created my own USB Protocol Analyzer (as well as one for PCI Express). They for sure had their work cut out for them.

My own 1480A USB 2.0 LS/FS/HS design was created between 2005 and 2009 in my evening and weekend spare time. Essentially, it was a massive effort required despite 20+ years of professional EE and CS experience. I found that there is a reason these things cost thousands of dollars....

I'm about to start raising funds on Kickstarter to upgrade the 1480A to a 1480B model. The updated model will incorporate lots of advanced features currently available in my 2500A PCI Express Protocol Analyzer design. My (preview) kickstarter campaign below contains a complete description of how the current 1480A USB Protocol analyzer works - if you are interested, take a peek (need to add a video before going live):

http://www.kickstarter.com/projects/itic/1589258766?token=f6d8fcbf

/John.
« Last Edit: August 15, 2014, 05:33:30 pm by John_ITIC »
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