Re: UI, I think realistically speaking the #1 priority is getting the hardware to do everything it needs to do, and then ship the devices to backers. I'm sure the software side will benefit from having more people willing to chip in with some help. But yes, munging the output into pcap format to feed it to wireshark is one of the more logical approaches.
(By the way, migen is awesome. If you know Python and you design RTL logic, you should try it.)
Well, I tried it. Tried to find an excuse to use it that is. Read the tutorial + user guide, but why would you want to use this, even if you do like auto-generated verilog?
I am all for new tools in the toolbox, but I didn't get an a-hah! moment when reading the docs... So maybe you spotted a nice usecase that I missed?
It's a bit hard to explain. For one, the metaprogramming is *awesome*. One of the things that bugs me most about verilog is how tedious it is to build high-level structures (things like generate statements and for loops are... rather limited). With migen, you can just use bog-standard Python to make a generator for as complex a design as you want. There are built-in classes to generate things like FSMs, buses (of various kinds and features), FIFOs (async and sync), register banks, etc. Migen also makes clock domain handling easier by encapsulating them into a class that synchronous statements interact with, and it also takes care of reset handling (e.g. you can switch a design from an explicit reset to an implicit FPGA config-time reset by changing one line of code, instead of having to change every always block and register initializer to take out the reset signal).
The other nice thing is that migen draws a hard distinction between the logic (what actually makes it into the device), which is conceptualized as synchronous and combinatorial statementss, and the Python that is really just a metaprogramming language around it. It's a lot closer to the way we think when writing digital logic (i.e. the "registers with clouds of combinatorial logic between them" idea), and it makes it much harder to write code that won't synthesize. I wrote the SDRAM core without a testbench at first, and I had made a single off-by-one-cycle timing mistake - it just worked after I fixed that. That just never happens with Verilog. I also like Python's class model better than Verilog's module model (with migen your entire design becomes one huge Verilog module, and it knows how to rename things so they don't collide within it - so you can freely name things in Python as you see fit).
And, of course, the way mibuild wraps the Xilinx tools and makes it possible to build designs without dealing with the ISE mess directly is great. Its way of defining UCF files is also more compact.