You can do this in DipTrace! While doing a PCB layout, you can create pads, silkscreen, mask, etc. right on the board, then select all the items, right click and select "Group into Pattern", now double click the new pattern, give it a name and click OK, then right click the new pattern and select "Save to Library" and it will be saved into the currently select library.
Can you elaborate further on this please Tim?
I have a quick question. I have added some long dual row headers to my board layout. They are used as "fingerling heatsinks" for some SMD mosfets on the board. I have been lazy & not added them to the schematic as they are just manually layed on top of a copper plane. Is there any way I can "Renew layout from schematic" without having these "fingerling heatsinks" automatically removed or reported as an error?
Okay, so Net Ties: Let's say I have a board and I want an analog ground (VSSA) and a digital ground (VSSD). I want to keep my grounds separate so digital switching noise doesn't creep into the sensitive analog plane. Now, I want these two separate ground planes to connect together at one point on the board, which forms a new net called GND. In software like Altium there is a "Net Tie" component that has three pins (or two, depending) that allows you to tie these separately named nets together.
Now, when you translate this to the layout, you'd have separate copper pour for all three nets; the VSSD and VSSA pours wouldn't connect to each other, but they would connect to the GND pour.
Right now in DipTrace, Novarm's answer is to "use a SMD resistor or create a new pattern with two copper pads touching to tie nets together". However, that doesn't really fly when I need to tie nets together that live on inner layers of a board (since on a 4 layer board GND is usually layer 2 of 4 in the stack) and you can't place patterns on inner layers!
Another example might be this: Say I've got an a WiFi module on my board and I need to lay out the antenna. I'd want to have a special copper pour that has a different clearance (say 15mil) around the antenna and RF trace, to maintain the correct impedance. Now this "RF_GND" pour should electrically be connected to the normal "VSSD" copper pour at the edges, as they should be treated as the same logical net. I'd use a two way net tie on the schematic to infer this.
Does that make sense?
As for your other question, here's what I do:
Create a new component in your library called "Assembly" and just have the symbol be a box with a single pin, don't attach a pattern.
Now, place this on your schematic, double click it, click attach pattern, select your "fingerling heatsinks" and in the double pane window at the top, click the pin of the component and then a pad on your pattern; repeat this for all the pads on said pattern (if there's more than one) so the single pin represents all pads.
Basically the "Assembly" component is a sort of universal component that I can use for one offs when quickly doing a schematic. I generally use it when I want to specify a heat sink or LCD with flat flex cable (since the FFC connector is actually what is on the schematic representing the LCD's connections, I still want the LCD itself to be on the BOM and perhaps have a silkscreen outline for it).
Hopefully that made sense.