Author Topic: Clearance Bug in Eagle 7.1 / 7.2  (Read 2604 times)

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Offline Ondre

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Clearance Bug in Eagle 7.1 / 7.2
« on: December 03, 2014, 04:00:14 am »
Hi everyone,

I've encountered a really annoying problem in Eagle 7.1 and also 7.2.

Here’s what I did:
Ages ago I started a PCB layout in Eagle 5.x. In the meantime I switched to Eagle 7.1 and made a few changes to the PCB. Today I made more changes, saved the file and ran the DRC. Now DRC suddenly tells me that there are tons of clearance errors. I checked the clearances manually and they are certainly within the specified rules. Even when specifying 0mil between adjacent tracks, the DRC still fails. I quickly upgraded to Eagle 7.2, but the problem still exists.

My backed up file from last week works fine with the same DRC settings from the DRU file.
Any ideas what’s going wrong here?

Best regards
Ondre
 

Offline Ondre

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Re: Clearance Bug in Eagle 7.1 / 7.2
« Reply #1 on: December 03, 2014, 06:07:16 pm »
Ok, problem solved :-)
It was a net class clearance violation. I surely didn't create them, but they were messed up. Maybe something that happend during the upgrade from 5.x to 7?
 

Offline 3p141592654

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Re: Clearance Bug in Eagle 7.1 / 7.2
« Reply #2 on: October 19, 2017, 11:35:43 am »
Happened to me too, with version 7.7.  Not sure what I did that changed the class clearances, but it cost me a few hours to figure it out.
 


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