Hi everyone,
I've encountered a really annoying problem in Eagle 7.1 and also 7.2.
Here’s what I did:
Ages ago I started a PCB layout in Eagle 5.x. In the meantime I switched to Eagle 7.1 and made a few changes to the PCB. Today I made more changes, saved the file and ran the DRC. Now DRC suddenly tells me that there are tons of clearance errors. I checked the clearances manually and they are certainly within the specified rules. Even when specifying 0mil between adjacent tracks, the DRC still fails. I quickly upgraded to Eagle 7.2, but the problem still exists.
My backed up file from last week works fine with the same DRC settings from the DRU file.
Any ideas what’s going wrong here?
Best regards
Ondre