Working out Footprint Issues in Eagle 7.7

[Xnke]

I mostly use eagle these days for RF work, it's easier than trying to do it in other programs, but only as long as I get my footprints configured correctly. In the past, I've always done the footprint modification in the actual board layout, adding polygons and vias for thermal use. I'd like to put that into some of the common packages I use, like the SOT-89 package that gets used for some MMIC amps, and the PowerSO-10 for the newer STMicroelectronics LDMOS power mosfets that I *really* like. (They are REALLY  nice for modern rigbuilding!)

So here's a new footprint I drew up, that has the top copper thermal vias and thermal pads layed out. It places the parts correctly, but the polygons drawn in the footprint editor seemingly can't be named and don't seem to inherit the pin name.



Here's an example of a board layout that I would like to use these in, but as you can see, the top and bottom copper fills follow the isolation rules, and my ground plane gets jacked up.



Does anyone know how to correct this, so that my RF and power device packages can have their minimum thermal footprints when I ask for them?

[rachaelp]

Hello,

You need to make sure the polygons for extending the footprint to a custom shape completely surround the centre of the SMT pad they are associated with, not just touching the edge. Then EAGLE automatically makes them part of the pad in the board editor.

Best Regards,

Rachael

[Xnke]

Rachel, they do exactly that. The central thermal areas completely surround the pad-but I did not remove the original SMD pad-is this the issue? That I did not remove the original pad?

[rachaelp]

No, the pad needs to stay there, EAGLE uses that to map the pins. Have you drawn it as a single polygon or multiple polygons? Are you sure it's a footprint issue and not something named wrong in your board? I assume you are expecting these thermal pads to be connecting to the copper plane they are currently isolating from? If so, the plane isn't connecting to any other components on the same net as it's isolating from them too so it looks maybe your plane isn't matching the net name on those parts.

[MarkL]

One way to do what I think you want is to first build your thermal areas out of SMD pads.  Turn off Thermals, Stop, and Cream for each SMD pad.  To help get the right final shape, you can round the SMD corners and angle them.  It's not straightforward, but you can probably get fairly close to the shapes that you want.  You're basically doing a fill of the thermal areas with SMD rectangles.

Then, embed the pads with drill sizes that you want to act as the thermal vias.  For each of the pads, turn off Thermals and Stop.

Note that you can overlay thru-pads and SMD pads as much as you want in the package editor and the DRC will not complain about it.

When you build the device, use the connection tool to append all the vias and pads associated with each signal (it looks like you only have one signal - ground) onto one pin using the ANY option (the little GUI icon with no connecting copper).  The ALL option also seems to work.

When you place the part onto a poured plane and have the aggregated pin on the device named the same as the plane, the SMDs and pads should just merge into the plane with no gaps.

I think this is what you want.  I tried it on v7.7.

[Xnke]

First thing I did was attempt to name the polygon and the SMD pads the same thing. The issue is that somehow, the SMD pads all got named "GND1" and the polygon for the copper fill "GND".

Now, I can not rename either of them, because "Can't Backannotate this operation. Please do this in the schematic!".

What have I done now? (Shoulda left it alone, Xnke, shouda left it alone!)

[MarkL]

Are you selecting the "only this Polygon" option when renaming?  The default is to rename "the entire Signal", which would give you that error if you enter a signal name that already exists (like GND).

If you look at the schematic, what is connected to GND and GND1?

If you can post your library and board I would take a look.

[Xnke]

OK-I'll have to consolidate the board libraries down to a single, but this library contains the parts and footprints I'm working on-the plan is to have RF-specific footprints in this library, but if I don't need the extra special footprint for whatever reason, just use the regular parts out of the normal libraries.

The file extension has been changed to .txt from .lbr, to make it uploadable here.

The parts in question are SGA-6589, and PD55025E. Both of these have vias and land patterns specific to heatsinking and RF performance, and both are giving issues.

I'll create a basic schematic and board file using both of these two parts and post it back up here ASAP-dealing with a frozen pipe situation over at my workshop.

[rachaelp]

I've just looked at SGA-6589 here is the list of issues:

1) You haven't added any of the pins for the through vias to the GND pin mapping. EAGLE won't see them as being part of the net so won't connect anything to them on other layers.
2) You polygons DO NOT surround the pins. EAGLE will not see them as part of the pin. It is a requirement of the custom pad shape feature than polygons completely surround the centre of the pad they are extending.
3) Also, you only have effectively one GND so why have two on the symbol? Just have one pin on the symbol and map both SMD pads and all the TH pads to that one single GND pin.

I've modified the part and attached. You might want to check the sizes of the polygons as I only did it quickly as an example.

[MarkL]

Here, try this.  This was created using the method I described above using multiple SMD pads.  I did it mostly by eye so the dimensions aren't exactly as you had them, so tweak them if you want.  I'm not making any guarantees as to correctness for your part - it's really meant to illustrate what I was saying.

I renamed the pads to add a little sanity.

I deleted the via underneath the tab.  This is referred to as "via in pad".  You can put it back if you want but I wouldn't recommend it if it can be avoided because the hole can wick solder out of the joint.  If you still want to do it you should check with your board fab and assembler.

Rachael - Your part did not work for me.  Perhaps 7.7 does not do the polygon merge thing you described.

EDIT:  Also, I didn't do anything with PD55025E or any other part.  Just SGA-6589.

[rachaelp]

Rachael - Your part did not work for me.  Perhaps 7.7 does not do the polygon merge thing you described.

Well that'll teach me not to check it properly! I don't know what the issue is, it should of worked as I used to create custom pad shapes back in the days of v7 too and they always worked. I'll check it out later and see what I did wrong...

[MarkL]

Rachael - Your part did not work for me.  Perhaps 7.7 does not do the polygon merge thing you described.

Well that'll teach me not to check it properly! I don't know what the issue is, it should of worked as I used to create custom pad shapes back in the days of v7 too and they always worked. I'll check it out later and see what I did wrong...

Sorry, looking at this a little more closely, it does appear the polygon pour belongs to the same signal as the enclosed pads.

However, what threw me is that there are thermals around the polygon pour, which I think is what the OP was trying to remove.

After playing with it a bit, it appears that the thermal attribute is inherited from the oldest pad placed within the polygon (at least on 7.7).  I don't see how that could be determined by looking at it except maybe via the XML, so the best policy is probably to turn off thermals on all enclosed pads.  If you do that, your part works as the OP desires (as I understand it).

Also, in order to prevent airwires from appearing between all the pads inside the polygon, the ANY attribute in the connection tool should be used.  At least they appear in v7.7 when the ALL attribute is used, which makes sense (although it could figure it out).

Your version modified below.

[rachaelp]

However, what threw me is that there are thermals around the polygon pour, which I think is what the OP was trying to remove.

I don't think the OP's issue is actually relating to thermals. It's not connecting at all and completely isolated because the polygons aren't inheriting from the pads because the polygons have been drawn incorrectly and are blocking the planes from connecting.

After playing with it a bit, it appears that the thermal attribute is inherited from the oldest pad placed within the polygon (at least on 7.7).  I don't see how that could be determined by looking at it except maybe via the XML, so the best policy is probably to turn off thermals on all enclosed pads.  If you do that, your part works as the OP desires (as I understand it).

Yes I agree, turning off the thermals on the enclosed pads is probably the right thing to do.

Also, in order to prevent airwires from appearing between all the pads inside the polygon, the ANY attribute in the connection tool should be used.  At least they appear in v7.7 when the ALL attribute is used, which makes sense (although it could figure it out).

Yep agreed, I didn't sort this because I was only focussing on the custom pad shape issue

Best Regards,

Rachael