Align in altium

[blueskull]

Hi, how can I align a component PRECISELY to grid? I used align to grid command, and it won't work. There is always a 0.5 grid residual error.

My pcb lib uses 0.025mm grid, metric unit, and my pcb doc uses the same standard. The aligning error varies from part to part, from approx. 0.0002mm to 0.0125mm.

The error won't affect the final board, because it is far smaller than process capability, but it drives my OCD crazy.



Thanks,
Bo

[T3sl4co1l]

Is the component origin the center, pad, or on the grid of the silk line shown?

[free_electron]

the part aligns to the grid from the part origin. Where is the part origin ?

Also a 0.025mm grid is to design substrates, not pcb's.
if you run it that close , prepare to get a lot of flac from the company that will make the board as they can't etch to that tolerance with standard copper ( 1oz / 35 micron)

at that precision you'll need to drop to 1/8 ounce copper and then plate up to 1/4. very few fabs can do that

[Christe4nM]

Using a 0.025mm grid for component placement is like using no grid at all: with such small steps it's like you can move anything anywhere.

If you want to satisfy OCD, for me a larger grid works better. For most simple SMD boards I use a 0.5mm grid for component placement with origins in center of a component's footprint.
Designator go on a 0.25mm grid.
Most of the time traces as well if the circuit has no need for smaller trace/space settings
Works a charm

[T3sl4co1l]

IPC recommends a grid of something like 0.5mm for placement, which I expect is to facilitate old PnP machines with poor control and tolerance, or whatever.  That always seemed rather blocky to me, but it seems to my OCD, it's far harder to align anything on a grid finer than 0.25 to 0.1mm.

Corner of the pad is a bizarre choice of reference, that seems to have no relation to the part, semantically or geometrically.  Traditional (also IPC recommended) centers are either center of pin 1, or part centroid (which is also the geometric center, so it looks good too).

Also BTW, it looks like you are placing silk almost right on top of a pad.  Most board houses will remove this completely, after subtracting both soldermask expansion and silk position tolerances from the desired pad aperture.  If you draw a full box type outline around the footprint, the silk edge should be at least 0.2mm from the copper edge.

Tim

[Bud]

  Traditional (also IPC recommended) centers are either center of pin 1, or part centroid

Does it have to be uniform across the board, I.e. all components referenced to pin 1, and how would pick and place machine know what origin was used?

[Psi]

Also a 0.025mm grid is to design substrates, not pcb's.
if you run it that close , prepare to get a lot of flac from the company that will make the board as they can't etch to that tolerance with standard copper ( 1oz / 35 micron)

How does a 0.025mm grid effect them?
As long as the board passes the pcb fabs clearance requirements i cant see the grid position mattering to them.

[T3sl4co1l]

http://electronics.stackexchange.com/questions/44883/designing-pick-and-place-friendly-cad-library-parts

This isn't bad.  Kind of old, seems to concentrate on wave much more, and tolerances correspondingly larger:
http://www.altronmfg.com/files/Board%20Design%20Guidelines%202003%20Rev-A.pdf

Tim

[free_electron]

Also a 0.025mm grid is to design substrates, not pcb's.
if you run it that close , prepare to get a lot of flac from the company that will make the board as they can't etch to that tolerance with standard copper ( 1oz / 35 micron)

How does a 0.025mm grid effect them?
As long as the board passes the pcb fabs clearance requirements i cant see the grid position mattering to them.

The problem comes when exporting gerber. Depending on what is chosen as format there will be rounding errors. Most fabs , even when you supply 2:5 will round down to 2:3 as their equipment can't handle it.  Remember that the fabs apply scaling to the data. Depending on the copper foil they use they may widen or shrink traces a bit to comlensate their etching process.

After file intake they run it against their rule checker. It may fail there. And you may get a call : sorry but this falls outside our fab tolerances.

It is not a good idea to design to such small grids if there is not a need to (like bga substrates). You need to understand the board process.

This happens too many times. People think that pcb design is just drawing some rectangles and that the fabs can do anything. That is not true. There are limits. Tha cad tools can do anything , the fabs are limited.

Measure with a micrometer, mark with chalk, chop with an axe ....  Futile.