Electronics > General PCB/EDA/CAD Discussions

Altium Designer: Why my polygon to via clearance rules ignored?

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javad2040:
hello guys.
I design the Data Acquisition system board that has ZYNQ FPGA, two AD9643 ADC, two DDR3, LAN 1Gb, PCI-e v2.0 and power components.
I use Altium Designer 18 EDA for designing the board and all high frequency rules (such as: length match, PCB stack up, trace width , ...) has considered and applied.
The characteristic of board is:
#layer : 12
thickness : 66.4 mil (1.68 mm)
Min. Line/Track Width: 3.543 mil
Min. Line/Track Space: 3.937 mil          
Min. Finished Diameter of PTH Hole: 0.2 mm

I define some Rules to check the space, width, length match of traces that are high frequency, and define the Rules to pour the Power and GND polygons.
The clearance of poly to poly in inner and outer(top and bottom) layers is 15 and 10 mil respectively; also i define Rules for poly to via clearance that in BGA components are 4 mil and others are 10 mil.
when the Rules applied all via catch the 4 mil for clearance . I change the priority rules but this problem is exist.
How to define correct clearance rules (poly to via) to pour the polygons according to special(my) style? 
Please help me to solve this problem.

regards,   
 
   

r0d3z1:
are you sure that 4mil is the real distance ? try to measure it on the gerber. I am not sure if you know that the gray area of vias pad is the area of top/bottom pad but you don't have it on the inner layer if the it is disconnected.
Otherwise, it looks like a priority problem, than right click on the vias, and use the "applicable binary rules" tool to debug the rules problem.

BrianHG:
Is it possible you have a feature similar to 'Optimizing Annular Rings of Vias in Inner Layers' for that via?
Switch to single layer view and cycle to the offending fill layer to see if the via is actually smaller on that layer.

Here is a explanation of how this looks and is usually automatically done when using true power planes:
http://www.eevblog.com/forum/eda/you-get-more-copper-between-padsvias-using-a-true-power-plane-instead-polyfill/msg1524124/#msg1524124

free_electron:
share your ruleset.

javad2040:
Thank you for reply,
my problem solved :
I use Room and define rules for it. The FPGA and DDR3 via has the 4mil clearance anad others 15mil.
best regards.

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