I've tried looking for that before, seems to be scant information.
http://www.hagtech.com/pdf/impedance.pdfThis has curves which may be useful. Doesn't look like the impedance goes low enough, which is a concern. A lower ratio may get there.
The limiting case for trace width --> infty is a slot line,
http://janielectronics.com/szamitasok/Transmission%20Line/Slot%20Line%20Calculator/janilab.phpdefined only by the gap between traces and the dielectric. (Obviously, for Ethernet which must use a TEM mode, the traces can't be infinitely wide, or returned to ground as in a slotted waveguide (finline); just assume that the impedance approaches this value for w >> h.)
This may require inconveniently wide traces.
The other option is parallel plate transmission line, which I can't find a damn thing on. The construction is simply placing the traces in the same locations, opposite layers. The problem is, every EE course uses this as an introduction to transmission lines, which yields only the very-wide limiting result. No one seems to explore the case with fringing fields.
If nothing else, you can construct the geometry and simulate it with something like ATLC2.
On a practical note, if the application is only 10/100Mb, that can literally run over coathangers. It's very tolerant to mismatch, and running traces that are good-enough will more than suffice, particularly if they are short. Traces of only a few cm or less will probably be fine at Gb too.
Tim