Flipped Differential Pair PCB Layout

[jeffr]

Hi All

I have a connector with 2 rows of surface mount pads next to the pcb edge. Connected to it is a differential pair thats flipped.
Because they are flipped and the traces need to pass under the top layer to get to the row next to the edge, I have two pairs of vias and traces on 3 layers.

The differential pair has speeds of 5Gbps.
I don't have much practice with high speed layout. Will the design in the picture have high speed signal problems? Is there a better way to layout this differential pair?

Thanks

[jeroen74]

I don't know if this going to or coming from an FPGA... some FPGAs allow you to set the polarity of the high-speed transceiver, or some FPGAs might even have auto-polarity. So if you swap the polarity in the FPGA, you can prevent the crossing in the layout.

[AlfBaz]

A while ago, I got a chance to play around with hyperlynx.
Using via's from top to bottom layers and the propensity for layout tools such as altium to place pads on non-breakout layers by default, I was amazed at the difference in signal integrity between having and not having pads on non-breakout layers.

Moral of the story, if you are going from top to bottom, make sure you remove pads on the inner layers for these vias

[jeffr]

Thanks! I'll only use the top and bottom layers then
In this project the traces are coming from a IC instead of FPGA so swapping the pins isn't possible.

Because the bottom layer is further away from the ground layer, if I use the same trace width on the bottom layer as the top layer will there be impedance matching problems?

[kfitch42]

CAVEAT: I am not a PCB guy

I might be crazy, but ... what if you put the ASIC on the bottom? You still need vias, but you don't have to cross the traces.

[DutchGert]

Thanks! I'll only use the top and bottom layers then
In this project the traces are coming from a IC instead of FPGA so swapping the pins isn't possible.

Because the bottom layer is further away from the ground layer, if I use the same trace width on the bottom layer as the top layer will there be impedance matching problems?

Well, you have to adjust your traces ofc.

If you switch layers also place ground return via's near the exsisting via's

Read thise: http://www.ti.com/lit/an/spraar7e/spraar7e.pdf
It covers all of the above

[John_ITIC]

Hi All

I have a connector with 2 rows of surface mount pads next to the pcb edge. Connected to it is a differential pair thats flipped.
Because they are flipped and the traces need to pass under the top layer to get to the row next to the edge, I have two pairs of vias and traces on 3 layers.

The differential pair has speeds of 5Gbps.
I don't have much practice with high speed layout. Will the design in the picture have high speed signal problems? Is there a better way to layout this differential pair?

Thanks

What I usually do is to route past the connector, make a 180 degree turn back and connect without swapping the signals.

[Monkeh]

What IC are these pairs coming from?

[jeffr]

The IC is a video transmitter. The connector is against the edge of the board and has a cutout under. There is not a way to get the traces in from the side or the back.
It is possible putting the IC on the bottom but it reverses the orders of the other pairs.

[AndyC_772]

It would do no harm to ensure that both traces at least have the same lengths on each layer, with vias in the same positions in terms of their electrical distance from the IC and the connector.

That way, even if you can't avoid swapping the pair, any distortion introduced by the vias at least has a chance of being equal and opposite between the two halves of the pair. It might tend to cancel out at the differential receiver.

[Robert Karl]

Maybe something like the picture attached? (Done on MS Paint-CAD, watch out Altium..)
I think that is kind of what John_ITIC was suggesting.

Also yes, it wouldn't be a bad thing to adjust trace width to account for different layer characteristics.

You seem to be a bit stuck with space, having pads to the right and a slot to the left.


PS. I am also not an expert in high speed. This is just my opinion.

[Rerouter]

Or to make it neater, maintain coupling, and keep the traces the same length, This?

[Robert Karl]

Or to make it neater, maintain coupling, and keep the traces the same length, This?

Looks nice Rerouter. However the way I understand it, he'd like to end up on the bottom layer (he didn't explicitly say, but that is how the original layout was).

If that is the case, then another pair of vias would be needed.

I'm curious, at what point does neatness and superior coupling trade off against having less vias/layer-hopping?

[Errmy]

When I route differential pairs (up to 100GHz) I make sure that there are no vias at all and the microstrip lines have a defined impedance of exactly 50 Ohms and the layout is as symmetrical as possible. Also using HF Substrate and 3D simulating this impedance. As far as I remember the HF characteristics of FR4 are not the best.

So is my question, is the impedance of the differential pair important? If yes, then there are some more challenges.

[Rerouter]

Then here we are with only 1 layer change,

To robert, for high speed less vias always wins, Unless you get very creative there will always be some form of impedence disturbance,

Coupling reduces the amount of noise that can get into a differential system, however a large bump in impedance can make far more noise,

In general on any design where high speed is required, I group very tightly around the fast components, to make sure that even if i screw with the impedance, that i try and stay under the magical 1/4 wavelength where possible, (impedance still matters, but the disturbances are attenuated faster as they have to traverse less transmission line before hitting a termination resistance)

[jeffr]

Those are great suggestions Robert and Rerouter. Thanks. (MS Paint will bankrupt Altium if this catches on )

The differential pair is designed for 100 ohm differential impedance. The traces are long (2 inches) because of the overall layout.
Now I question the dimensions of the vias to not effect impedance.
The fab has a minimum 10 mil drill size. Is there a rule of thumb for minimum via pad diameter?

[jeroen74]

The fab has a minimum 10 mil drill size. Is there a rule of thumb for minimum via pad diameter?

The PCB fab can answer that question; it's called the annular ring and they have a minimum spec for that.

[Feynman]

Well, the most important questions are: What rise times are you dealing with and how long is the transmission line?
Chances are that you don't have to bother at all with high-speed issues. However "5Gbps" indicates that the rise times are way below 1ns, so the chances are not too good

Further questions: Is the differential pair significantly coupled at all or are odd and even mode impedance equal (consult a field solver)? If the differential pair is not coupled, you only have to worry about the single ended impedance discontinuity of each line due to the vias.

The inductance of vias can be compensated with additional capacitors on both side of the via. If the resulting impedance of the via inductance and the compensation capacitors equal the transmission line impedance, the via is "invisible" for high-speed edges.

Of course, keeping both traces the same length, is always a good idea.