How do you denote a plugged and plated via?

[ocset]

Some of the vias on our PCB are thermal vias, and they are to be plated over with copper, and plugged with epoxy.
However, other vias on the same PCB are normal vias, and are not to be plated over, and not to be plugged.
How do we denote this to the PCB assembler? The information doesn’t appear on the gerbers.

[voltsandjolts]

That's a question for your PCB manufacturer, assuming they offer selective plugging.

[ocset]

Any reasons NOT to plug other vias?

No reason , other than it (might) cost more.
Not all the vias on the pcb need to be "plated and pugged".

At the moment,  we have just put a "topplate" and "botplate" layer , and "patched" this on the pcb in various places, over the vias that need plugging and plating, and will tell the pcb manufacturer to please plug&plate all vias in  those patchs...but this seems a slap-dash way to do it, and we wonder what is the professional way?

[T3sl4co1l]

Epoxy plugged vias wouldn't seem to do much for thermals; don't you want them to fill with solder?  Is the plug resin a thermally conductive epoxy?

As mentioned, there is no official formatted method to denote this; it goes on the fab drawing.  PCB fabs -- the good ones anyway -- do in fact read all the notes and try to comply with as many of them as possible.

Tim

[ocset]

Thanks yes we would prefer filled with solder, but  i believe the cost is higher than epoxy....however, will check, because just maybe au contraire.

[Psi]

When i got some PCBs with plugged vias i only needed 10 or so done, but they said it would cost more than just getting all vias plugged.
Since they would have to do an extra step to mask some but not others in the plug stage.