How much should I worry about vias on RMII signals?

[SirNick]

I'm laying out a board with an LPC4078-100, using its internal Ethernet MAC to drive a Micrel KSZ8041RNL 10/100 PHY via RMII.  The Micrel takes a 25MHz crystal and generates the 50MHz RefClk internally, which is fed back to the MAC.

After reading some application notes and layout guidelines, vendors strongly encourage not using vias on RefClk, TX0/1, and RX0/1 in particular.  However, because of part placement and relative pin order between the MAC and PHY, some of these cross each others' paths.  I don't know that I could lay out these parts without using ANY vias.  How many kittens will die?  Is that just life, or should I move mountains to avoid it?

Here's a screen shot of the work in progress, with everything around the Ethernet part that isn't directly involved de-saturated for clarity.  It is a 4-layer board (Component, Vcc, Gnd, Signal / Chassis Gnd) but the middle layers are hidden here.  Note, I haven't added series resistors to the high speed lines yet, that's next on the list.

FWIW, this is a hobby project, and my first time implementing Ethernet (and USB).  I'm just trying to learn the ropes of high(-er) speed design.  I'm not super concerned with passing EMI compliance testing, although I'd like to develop good habits.  Mostly, I want to get as much right as possible on the first try.  This is looking to be about a $200 board to fab (plus parts), so I'm trying to avoid having to spin a half dozen iterations due to poor design choices.

Thanks to anyone willing to give it a glance and throw some constructive criticism my way. 

[jahonen]

I have a hunch that at those edge rates that your processor and PHY generates, vias are not going to have any significant effect. But if one is pedantic, then jumping to the opposite side of the PCB is the worst thing that one can do to the signal This is because the return path is then broken and it must traverse through all those layers, too. However, in practice that seldom causes problem on casual edge rates. One improvement that could be done to mitigate harmful effects is to put a stitching capacitor between these two reference planes (or several) near the signal via.

The most important thing that I would worry about is the common clock timing used by both PHY and the MCU on the RMII interface. I'd check that very carefully so that there are no timing problems. So read PHY and MCU datasheet RMII timing specifications very carefully and do the maths.

Regards,
Janne

[SirNick]

OK, thanks.  I guess I'll optimize, add series resistance, and accept a via wherever it's necessary.

I don't quite understand the part about stitching caps and reference layers.  Do you mean I should put a cap near the signal via, with one side tied to Vcc, and the other to ground?  (So, a decoupling cap but without a load on it?)  Or with one (or both) sides attached to the signal trace?

Timing compatibility never even occurred to me until a couple of days ago when someone referred to the LAN8720 datasheets being particularly thorough with layout recommendations.  It mentioned several times that the RefClk output "is not RMII compliant" and that any potential compatibility should be considered a fortuitous coincidence.    I had previously assumed RMII MAC + RMII PHY = Happy Times.  I'll settle down with the datasheets and compare timing diagrams.  Hope it works out, it would suck to have to swap parts now, but at least I found out before spinning a PCB.  Thanks for mentioning that.

[Stebanoid]

Connect two reference layers by cap to create a return path for ac current.
See picture with PCB layers slice below.

[AndyC_772]

Use series terminating resistors on all the RMII lines. 33R placed close to the driving end of each trace is a good start.

Ethernet PHYs can be noisy, and it can help to flood the top layer with a GND plane in the region around the PHY and connector - as well as having a solid GND plane on layer 2, of course. It's more an EMC issue than a functional one.

Timing really isn't that much of a problem on RMII. It's always a good idea to compare the setup & hold timing requirements in the data sheets, but RMII usually has good margins.

Make sure the Micrel PHY gets a clean reset signal. IIRC there's a note in their data sheet recommending a large capacitor on reset, in order to ensure a reset pulse that's wide enough. This is bad advice, because what it actually means is the reset signal hovers around the 0/1 threshold for a long time, and any noise it picks up at this time can result in multiple 0-1-0 transitions, the result of which is that it doesn't actually get reset properly. You're better off putting a small capacitor next to the PHY, and driving a wide, valid reset pulse directly from your MCU.

[SirNick]

Hope I'm not beating a dead horse here, just trying to get the most from this advice.  I understand the concept of the stitching cap now.  The board is already covered in decoupling caps -- 100nF mostly, with a few ceramic 1uF to 22uF as needed.  In particular, there are a few (100nF) caps in close proximity to the RMII signals, both on the PHY side and MAC side.  I don't mean merely "on the same chips", but actually in the same region of PCB as the signal path between the two.  Is there much to gain by having them within a few thou of the signal llines (or their vias), or should it be covered well enough already?  Just trying to weigh the benefit vs. the fact that the board is fairly densely populated as-is (understanding of course that this gets into the realm of tongue-angle tweaking, and may not be subject to generalisms).

Andy:  Thanks for the comments.  I did notice the reset cap suggestion, and it seemed maybe a bit counter-productive to me, so... well... I kind of ignored it.  (Glad to see that hunch may have been correct.)  The reset pin is pulled up to Vcc (held in reset) by a nearby resistor, and controlled by a GPIO pin on the uC.  I intend to specifically bring it out of reset as part of the init code rather than relying on power-on reset and RC timers.  I do not have a cap on that line, though.  It's being driven low by a fairly short and direct trace back to the uC.  Am I likely to see transients large enough to cause spurious resets (while allowing otherwise normal functionality) considering the low-impedance current sink at the GPIO pin?  Not sure if this is relevant to PHYs in particular, or if this should be standard practice on vital control pins that are typically at steady DC levels.  I've been getting away without so far... luck, or OK?

[AndyC_772]

Series terminate the reset line and you should be fine.

It's always the edge rate that matters when it comes to determining whether or not you need to consider transmission line effects and termination, not the number of transitions per second. You'd be amazed how many engineers don't really understand this.

[SirNick]

Well, edge rate and period do become correlated as frequency increases.    Not sure I would've thought of adding series resistance to a reset line either.  I should probably start paying attention to things like the slew rate characteristics of the micro, and reset pin hysteresis.  Stuff I've always taken for granted.  I guess that's the difference between engineering and Arduino projects.    Thanks again.