Looking for a logic modeling / simulation tool

[Sigmoid]

Hey

I'm looking for a modeling tool that would help me quickly brainstorm and test discrete digital networks based on 4000 series chips.
Mainly I'd like to see if my ideas are even humanly feasible, in terms of chip count. At this stage, I don't want to mess with a full-blown eda, and as far as I understand, there is no synthesis engine that would translate Verilog into discrete MSI-based logic - I did learn some Verilog back in the university, and I understand that would be the "pro" approach, but I'm slightly wedded to discrete MSI chips at this stage. If someone knows of such a synthesis engine, please do bring it to my attention.

There are quite a few logic modeling / simulation tools, and some that I had a look at were completely useless for anything beyond grade school demos. Ideally I'd need a wide range of components such as PISO and SIPO shift registers, the ability to define buses, etc. I prefer free as in free speech, but free as in free beer (or a non-exorbitant cloud subscription) wouldn't be bad either, if it's worth it.

Thanks a lot

[PCB.Wiz]

I'm looking for a modeling tool that would help me quickly brainstorm and test discrete digital networks based on 4000 series chips.
Mainly I'd like to see if my ideas are even humanly feasible, in terms of chip count. At this stage, I don't want to mess with a full-blown eda, and as far as I understand, there is no synthesis engine that would translate Verilog into discrete MSI-based logic - I did learn some Verilog back in the university, and I understand that would be the "pro" approach, but I'm slightly wedded to discrete MSI chips at this stage. If someone knows of such a synthesis engine, please do bring it to my attention.

There are quite a few logic modeling / simulation tools, and some that I had a look at were completely useless for anything beyond grade school demos. Ideally I'd need a wide range of components such as PISO and SIPO shift registers, the ability to define buses, etc. I prefer free as in free speech, but free as in free beer (or a non-exorbitant cloud subscription) wouldn't be bad either, if it's worth it.

Hmm - you are probably best to look at CPLD design flows.
The fitter report files from those, usually include the binary equations, and those you can visually map onto MSI parts, if you want to.

Lattice CPLD flows have reasonable flows and reports, as do Xilinx.
You could also look at  Atmel/Microchip WinCUPL.  https://www.microchip.com/design-centers/programmable-logic/spld-cpld/tools/software/wincupl

That's simpler than verilog, so is closer to Logic MSI to start with, and it has MSI macros, and is much smaller download than the full Verilog suites....
The functional simulator is also ok for testing before building.