the top layer has many nets and some of them are sensitive nets as you see above.
the second layer is the ground layer. but under these sensitive nets should be ground free!
3rd layer is the power layer.
4th layer is the solder side.
If I want to pour ground polygon in the second layer, this sensitive area will not be ground free! bcoz the nets are in the top layer and I'm in the second layer!
Hi,
I believe that sometime some pictures may be of better help than a lot of words.
Let's assume that you are using a 4 layer board.
The layer stack is set as this:
- TOP layer (signal layer)
- GND layer (plane layer)
- PWR layer (plane layer)
- BOTTOM layer (signal layer)
Signal layers are layers on which you lay traces and polygons and so on. Those are positive layers which means that wherever you see color (polygon pour, fill, traces etc) you will have copper on PCB.
Plane layers are layers meant to serve as a connection for ground nets and power nets. Those layers are negative layers which means that whenever you place "something" (trace, polygon pour, fill etc) in that place occupied by that element, there will be a lack of copper on PCB.
So, what you want is that under the region on top layer occupied by your marked components, on the GND plane, to have a void in the copper, a lack of copper.
This can be obtained by placing a copper fill on the GND
plane under that TOP area. But the GND plane being a "plane" and therefore a negative layer, by placing a "copper fill" in the end you get a void in the copper.
Please see the 2D view of such a board in the attached 2D.png
In the 3D view of such a board found in the attached 3D.png, you can sort of see the copper void under the area with the "opamp".
Attached is the Altium 18 PcbDoc file that I've setup and used to get those pictures.
LE: I've added also a picture where I removed all the copper on the PWR plane (by placing a copper fill big as the board) and in the 3D view you can see that the copper is removed by placing that copper fill on GND plane.