OrCAD/Allegro : ReAnnotate REFDES without affecting layout?

[Pack34]

I'd like to reannotate my schematic but the last time I did this after the layout has been performed it seemed to break the component locations. Meaning that any component that changed REFDES was no longer placed and had to manually re-place the affected components.

Is there a way to prevent this from happening or am I going to need to manually update the REFDES in the schematic by double-clicking on parts and changing their values?

[Alex Eisenhut]

You got me there. I'll have to look into it, I guess you're asking for Capture, right? The native Concept tool handles this correctly, but is maddening to use otherwise.

[Pack34]

Yes. Capture. If you use the re-annotate feature in capture, export a netlist, then import the logic into Allegro all of the components that changed REFDES are unplaced.

I decided to do it in chunks to make the re-layout easier and apparently if you just rename the parts manually it seems to work fine.

[Alex Eisenhut]

I think you need to back annotate from Allegro back to Capture first.

I've never had to reannotate in Capture. I can dig into it at work in my spare time.

[U96]

Hi,

What you do is the following:

1. Create a netlist of your current schematic and load it into your PCB. (make sure the "device/net/pin name char limit" is set to 255 in the 'setup' menu of the "create netlist" window)
2. in Capture, go to the Annotate menu and select  'Unconditional reference update'.  Also tick the 'REFDES control required' box. In the table which becomes visible choose your start and end value so that ALL refdesses are to be new ( nothing that will be assigned can be already in the current design.)  so for instance  Start value 10000 and end value 20000.
3. i'm not fully sure about this step, but i always use it when i have to perform this task:  enable the box "Preserve designator"
4. create a netlist of this newly annotated schematic and load it in the PCB.  no components should be removed from the board
5. now go to your schematic and do a new annotation of all refdesses the way you like. (make sure NO refdesses are reused from the range earlier specified (10000 to 20000 in this case)
6. create netlist and load in the PCB.  >> done

Allegro tries to match new/changed components to the pcb based on REFDES.  by doing it like above we force allegro to other methods of matching. (some internal referencing)

Greetings!

[jsvirzi]

This worked like a charm. Thank you for the small details about how to make it work.