Signal levels aren't very much (fractional volt?), though impedances are kind of low around the test part. So it makes sense to have some ground stitching around there, but one via every mm or less is unnecessary -- this isn't 20GHz! Instead, heavier traces will do more benefit, reducing the ESL of the path. (A proper ~10 ohm transmission line would be huge, probably 1cm+ wide, so you wouldn't even be able to implement that here. Anything smaller will show up as inductive, so that's pretty much what you're limited to.)
So the parts of the sense trace that are within the planes aren't terrible, they'll be inductive, but maybe that's not a problem. But then you have them leave the ground plane altogether, as if at line potential! You have many times more inductance in the gap between traces there than you do along the carefully stitched paths. There's no such thing as line voltage here (or ESD or EMC, for that matter), so no need to pull back the plane and make things worse.
Some of the routes are funny looking, like C19 to C6: why does the trace dip under, just to pop back up a few hundred mil later? Might as well help minimize the routing -- you can always add more stitching vias later.
ESD, EMC: I guess C15 is intended to block DC into the circuit, but are you intending that this thing be able to test an accidentally charged capacitor? That's pretty nasty. IC5, IC6, R14, even D1/D2 are probably all toast after such a transient. Same for ESD, beyond the 4kV the LTC6244 is rated for (and depending on internal diodes is risky at best).
Likewise, any external noise (EMC, RFI, etc.) will be rectified and sensed as reduced ESR. The general susceptibility shouldn't be too bad (nearby electric fields, for example, won't have a very easy time pulling around <1k loaded traces), but a cable of the right length plus a nice little radio source (it could be a powerful radiotransmitter, or a handheld, or even a damned GSM cellphone -- blip blip blip!) and your measurement is bad.
Also, I expect you aren't interested much in ESR below 3 ohms, since that's about what C15 limits things to (by reactance, not resistance).
More stitching: it's applied inconsistently. As long as there's no floating patches, this probably doesn't even matter, but it looks odd. The trace from R16 to D3 for example has several, while the power trace near SL2, or the traces between IC1 and R3-R5, have little or none.
For general use, my feeling is, use a 12 mil i.d. via, spaced every 400 mil or so, along a group of traces. Traces of similar purpose are grouped as buses to minimize space and stitching. (Of course, some traces you don't want together, and should be routed separately.) At the intersection of two such traces/buses on different layers, try to make the intersection 90 degrees if possible, and place stitching vias in the inside corners around the crossing. Finally, inspect the negative space that is the ground pour itself: anywhere a peninsula is hanging out, either reshape it to a bulkier outline (by moving around nearby traces), or tack it down with a via. Example: the patch between R4 and R5, where the trace to R5 hooks up and away from the others a little sooner. Those traces could be routed tighter until the last possible place (the trace to R4 could even enter the pad sideways, and the trace to R5, hugging tightly on its way up), or another via added near the point where the traces diverge (the divergence could even be exaggerated, by pulling back the R5 trace even further, enough to place a via in that crotch between the R4 and R5 traces).
Similarly, the gap near SL2 is ugly, and could be filled in simply by pulling that fat trace over (it doesn't have to leave the polygon at C3 in the middle, it could hug the side).
There are also some voids near components, such as D3 (ground doesn't fill between the pads?), R12, R10 and a few others. In those instances, I like to have the traces hug as closely as possible to minimize the excluded area, but they should be able to fill from the polygon anyway (why are the footprint pads so close together?).
Regarding the power supply, why use two 2.5V regulators? Why not invert the 2.5 the first time? You'll also get longer battery life using a switching controller, which need not be fancy: you can get small, quiet, low power (and low quiescent) chips for the purpose. Or if it's always a 5.0V source, who even needs that, just use a divide-by-two style charge pump IC! Or who needs ground at all, better still: add a virtual ground and connect the input to +2.5 and -2.5V! (Even with the battery controller and all, you can still do this, it'll just be returned to -2.5V instead of "GND".)
The supplies appear to be quite well bypassed -- all the caps are about as close to 'point of use' as possible, and the routes enter the cap first (kinda-sorta shielding noise from the IC).
I will add a note: anywhere you have two or more ceramic caps separated by a trace, you have a series LC resonant circuit (remember, the Cs act in series, so the effective capacitance that resonates is smaller than either individual cap). You can estimate the trace inductance and capacitor ESR, and after some waving of hands, come up with a reasonable guess at the damping characteristics. Guessing here, it's probably fine. The traces are short, and the capacitors are reasonable values, so the resonant impedance should be small, comparable to the ESR. It's not like there's much noise here (the charge pump I think will dominate), let alone much sensitivity to it (the sensed signal is relatively large, 10s of mV or more I think?).
So, all in all, not terrible. I don't see any glaring dumb mistakes -- it will work as advertised, at least away from radio transmitters, and electrolytics with excessive residual charge.
Many of these notes are somewhere between "well, so what" (e.g., outside of RF, who really cares how well ground is stitched?), and outright personal preference (as long as the trace gets there in a timely manner, who cares how it's routed?). So, despite the quantity written above, don't read into them very much!
Tim
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