PCB review request

[EK701]

I would appreciate any feedback on the following PCB.  The board size is to fit a specific enclosure.  This is a prototype board, so I have quite a few test points included.  The separate ground plane area on the bottom near the center is for analog ground.  AGND and GND are only tied together with FB3.  I probably went a bit overkill on the width on most of the power traces, but I don't think there is any harm there.

Signals on the board are UART serial, SPI, I2C (1MHz), USB, 3V3 analog, and 3V3 digital.  The device in the upper left is a Bluegiga WF121-A WiFi module.  The device in the upper right with no ground plane under it is a LSM9DS0 9DOF sensor.  The two devices in the middle with no ground plane underneath are a 16MHz crystal (Y1) and a 32.768MHz crystal (Y2).

I kicked around adding a ground plane area on the top layer for the open areas, but I'm not sure it's really needed or or benefit.  Nothing on the board is autorouted.  It passes a DRC check using OSH Park DRC rules (with a few exceptions for wire size where necessary).

I've attached an image of both layers and images of just the top and just the bottom layers.  Any feedback is appreciated!

Thanks!

[EK701]

Anyone?

[Christe4nM]

Hi EK701,

I saw no one commented yet, so let me tune in. Overall you’ve made a good start I think. For example I really like that the bottom layer is so clean with hardly any tracks running through it. I’d gone 4-layer with that MCU already I think, but you prove that that’s not really necessary. At the same time I think you might have missed certain things, so sit back, take a coffee for here it goes

•   The first thing I noticed was the isolated plane just above the MCU. THE biggest rule when isolating part of a plane is: “Absolutely NO trace crosses the gap”
So in your case: every trace that has nothing to do there must be routed around. In addition, I see that that isolated section is connected to some MCU pins. In that case extend the isolated plane to include those pins as well. Anything else getting in or out should be power or GND only and must cross the gap by way of a ferrite bead. (note that sometimes signals do enter a completely isolated plane, but then trough ferrites or common mode chokes. Preferably signals enter directly into the plane from an IC pin or connector)

•   Crystals especially require a ground plane directly underneath if possible. That way high frequency noise currents are coupled into the plane and have a fast way back to their source. So really do put a ground fill under them. If possible that can be done on the top layer too, with a few vias to the bottom ground fill or plane.

•   While on the topic of ground plane, is there a specific reason to remove the plane under the 9-DOF sensor? If not just put it there. A general rule of thumb is that a plane is better than no plane. (note the ‘in general’ and ‘rule of thumb’).

•   Any ground fills on your top layer are best connected to your bottom layer. At least in their corners. Sometimes flood filling can lead to floating fills, and they’d better be removed if they can’t be stitched with one or more vias.

•   C9 to C12, are they the power supply decoupling caps for the MCU? If they are, and I remember the Freescale Kinetis correctly, they should each be close to a pair of VCC/GND pins on the MCU. I usually place them first. If routing of nearby traces requires it, I move them a bit further out, but only as far as really needed to route adjacent traces. Also, use at least one via to your ground plane per cap. Even better is to place two vias on each side of the pad.

•   My personal preference is to place all components as such as to minimize the need for routing them partly on another layer. That becomes harder if connector locations are predetermined of course. Looking at the bottom layer you did a good job trying to minimize crossing the ground plane.
In the case of the Display connector you have 4 signals that need to cross each other to get to the MCU. I trick I use in such a case is to try an route them right at the connector pads in such a way they leave in the order as they need to arrive at the MCU. For example you could try to route the trace from pin 2 upwards first, then right, and down between pins 4 and 5.  Leave enough room and with the same trick route the trace from pin 4 upwards, then left, and then down between pads 2 and 3. If I’ve seen it correct your four signals now don’t have to cross anymore. Same trick could be done U3 if you wish: route the two signals to the left first, then down and let them leave at the bottom right corner. Now their order is reversed and crossing is not needed anymore.

•   Sharp angles in copper are (can be) a problem when manufacturing the PCB. Try to make sure every possible corner is at least 90 degrees. For example on R3, top pad the trace leaves at a quite sharp angle. Consider routing the trace “due north” a bit first before bending. The same applied to the bottom left pad of the GPS chip, and to some extend to the bottom pad of R3.

•   On to USB. USB can be considered a high speed signal. You want those traces running on one side, and one side only. Best is to route those signals first. If possible in Eagle (if I interpret the EDA looks correctly), try to route them as differential pair with a differential impedance of 90 Ohms. (bit hard on two layer, but if you’re in the ballpark for a hobby project you could be fine) R6 and R7 must be placed as close to the MCU as possible, as they terminate the high speed transmission line.

•   Just below Y2, is that a cap? If so, consider routing the larger trace directly to its pad, and then from the pad to the MCU. This minimizes trace resistance and inductance between the signal/power line and the cap. Same for C14 and 3v3 the lines.

•   Finally, just a matter of personal preference. In your power supply you could work with ‘areas’ instead of traces. Again, this is probably just personal preference: you could for example draw a fill/polygon between the fuse (?) D3 and inductor 07HVP.

So there you have it (phew ). I really hope this helps you. As I said in the beginning, I might reconsider two-layer for such a board as you show that it's fine to do so. But once you’ve done four layer, and can just stitch ground and power to their respective planes directly… …let’s just say I’d really miss that. But we’ve been spoiled: in the old days it was two layer only and they made it work and for very complex boards too…

Good luck,

Christean

[EK701]

Hi EK701,

I saw no one commented yet, so let me tune in. Overall you’ve made a good start I think. For example I really like that the bottom layer is so clean with hardly any tracks running through it. I’d gone 4-layer with that MCU already I think, but you prove that that’s not really necessary. At the same time I think you might have missed certain things, so sit back, take a coffee for here it goes

Thank you!

•   The first thing I noticed was the isolated plane just above the MCU. THE biggest rule when isolating part of a plane is: “Absolutely NO trace crosses the gap”
So in your case: every trace that has nothing to do there must be routed around. In addition, I see that that isolated section is connected to some MCU pins. In that case extend the isolated plane to include those pins as well. Anything else getting in or out should be power or GND only and must cross the gap by way of a ferrite bead. (note that sometimes signals do enter a completely isolated plane, but then trough ferrites or common mode chokes. Preferably signals enter directly into the plane from an IC pin or connector)

If understand you correctly, I should extend the AGND plane (the isolated one) to included the associated MCU pins?  The only thing I intend to cross the plane is the ferrite, FB3.

•   Crystals especially require a ground plane directly underneath if possible. That way high frequency noise currents are coupled into the plane and have a fast way back to their source. So really do put a ground fill under them. If possible that can be done on the top layer too, with a few vias to the bottom ground fill or plane.

Yep, a screw up on my part.  I thought I read that there shouldn't be a ground plane under the crystals.  After seeing your comment, I went back and looked again and it's no signals under the crystal and must have a ground.  I'll fix it. 

•   While on the topic of ground plane, is there a specific reason to remove the plane under the 9-DOF sensor? If not just put it there. A general rule of thumb is that a plane is better than no plane. (note the ‘in general’ and ‘rule of thumb’).

The manufacturer recommends no ground plane under it as it can effect the sensor.

•   Any ground fills on your top layer are best connected to your bottom layer. At least in their corners. Sometimes flood filling can lead to floating fills, and they’d better be removed if they can’t be stitched with one or more vias.

I think I'll do a ground fill on the top layer, too.  Hopefully that will resolve any potential issues.

•   C9 to C12, are they the power supply decoupling caps for the MCU? If they are, and I remember the Freescale Kinetis correctly, they should each be close to a pair of VCC/GND pins on the MCU. I usually place them first. If routing of nearby traces requires it, I move them a bit further out, but only as far as really needed to route adjacent traces. Also, use at least one via to your ground plane per cap. Even better is to place two vias on each side of the pad.

I'll see what I can do.

•   My personal preference is to place all components as such as to minimize the need for routing them partly on another layer. That becomes harder if connector locations are predetermined of course. Looking at the bottom layer you did a good job trying to minimize crossing the ground plane.
In the case of the Display connector you have 4 signals that need to cross each other to get to the MCU. I trick I use in such a case is to try an route them right at the connector pads in such a way they leave in the order as they need to arrive at the MCU. For example you could try to route the trace from pin 2 upwards first, then right, and down between pins 4 and 5.  Leave enough room and with the same trick route the trace from pin 4 upwards, then left, and then down between pads 2 and 3. If I’ve seen it correct your four signals now don’t have to cross anymore. Same trick could be done U3 if you wish: route the two signals to the left first, then down and let them leave at the bottom right corner. Now their order is reversed and crossing is not needed anymore.

Thanks, I'll do that!

•   Sharp angles in copper are (can be) a problem when manufacturing the PCB. Try to make sure every possible corner is at least 90 degrees. For example on R3, top pad the trace leaves at a quite sharp angle. Consider routing the trace “due north” a bit first before bending. The same applied to the bottom left pad of the GPS chip, and to some extend to the bottom pad of R3.

Will do.

•   On to USB. USB can be considered a high speed signal. You want those traces running on one side, and one side only. Best is to route those signals first. If possible in Eagle (if I interpret the EDA looks correctly), try to route them as differential pair with a differential impedance of 90 Ohms. (bit hard on two layer, but if you’re in the ballpark for a hobby project you could be fine) R6 and R7 must be placed as close to the MCU as possible, as they terminate the high speed transmission line.

I had a hard time with the USB, as it will only be used rarely in this device.  I'll fix R6 and R7.  I'll see what I can do about the other issues.

•   Just below Y2, is that a cap? If so, consider routing the larger trace directly to its pad, and then from the pad to the MCU. This minimizes trace resistance and inductance between the signal/power line and the cap. Same for C14 and 3v3 the lines.

Will do.

•   Finally, just a matter of personal preference. In your power supply you could work with ‘areas’ instead of traces. Again, this is probably just personal preference: you could for example draw a fill/polygon between the fuse (?) D3 and inductor 07HVP.

So there you have it (phew ). I really hope this helps you. As I said in the beginning, I might reconsider two-layer for such a board as you show that it's fine to do so. But once you’ve done four layer, and can just stitch ground and power to their respective planes directly… …let’s just say I’d really miss that. But we’ve been spoiled: in the old days it was two layer only and they made it work and for very complex boards too…

I thought about a 4 layer board, but the version of Eagle I'm using only allows for two layers.  I've been intending to switch to KiCAD or gEDA, but I started this in Eagle.

Thank you very much for your input.  I really appreciate it!

Eric

[Christe4nM]

•   The first thing I noticed was the isolated plane just above the MCU. THE biggest rule when isolating part of a plane is: “Absolutely NO trace crosses the gap”
So in your case: every trace that has nothing to do there must be routed around. In addition, I see that that isolated section is connected to some MCU pins. In that case extend the isolated plane to include those pins as well. Anything else getting in or out should be power or GND only and must cross the gap by way of a ferrite bead. (note that sometimes signals do enter a completely isolated plane, but then trough ferrites or common mode chokes. Preferably signals enter directly into the plane from an IC pin or connector)

If understand you correctly, I should extend the AGND plane (the isolated one) to included the associated MCU pins?  The only thing I intend to cross the plane is the ferrite, FB3.

Yes and no. Yes extend the plane, no I think FB2 (?) should cross too, as you'll need filtered power inside.

To clarify with example:

From what I recognize you have a temperature sensor there, which is connected to the MCU's ADC. And I know that the Kinetis has a separate Analog VCC and Analog GND which is problably located at the neighboring pins right?

Let me show you an example from a board I did. Mind, it's four layer, but the principle is the same. (attached). I used the reference design of the MK20D72 tower board, as shown in the circuit diagram to the right.

If you look at the PCB section: TOP left is part of the MCU (100LQFP). You should clearly see the black isolation between all copper on all layers. There is not a single trace that crosses that isolation. Bottom right, outside of the screen capture was my connector, still within the isolated plane. As this is 4-layer I went from MCU pin directly to the bottom layer (not shown), still inside the iso-plane.
Now if you look at the bottom left there are only two components crossing the gap: a ferrite from MCU_3V3 to VDDA and a ferrite from system GND to VSSA. Directly above two caps where placed for analog power filtering/decoupling. Again, as this is four layer they are via'd directly to the analog gnd and analog power planes. The components to the right take things a step further to get a clean reference for the ADC. A bit overkill probably.

The point is: only power and gnd cross the gap via a ferrite to get clean power and ground for the analog section. Everything inside the isolated analog plane is only powered and 'grounded' to that filtered 'clean' power + gnd. The plane is extended to include the analog MCU pins as well.

Since my board was 4 layer, the analog signals are going directly to the bottom layer by a via (second screen capture), but stay withing the isolated section.

Back to you:
get power into the isolated plane through a ferrite. Get the isolated analog ground connected to system ground with a ferrite. Those two components cross the gap.
power the sensor from the clean analog power, do the same with the mcu analog voltage and ADC reference voltage. Don't forget to decouple both. (100n should do here)

Well, hope that helps!

Attached:
Image 1: screen capture of PCB with Top layer copper (blue) and ground layer (brown) + circuit mockup
Image 2: screen capture of same PCB area with power layer (blueish) and bottom copper (red)

[EK701]

The point is: only power and gnd cross the gap via a ferrite to get clean power and ground for the analog section. Everything inside the isolated analog plane is only powered and 'grounded' to that filtered 'clean' power + gnd. The plane is extended to include the analog MCU pins as well.

Thank you for the examples.  One question - I have two signals that I want to make analog measurements on.  The first is the TMP36 temperature sensor.  That is the connector at the top of the isolated plane.  The second is I want to measure the voltage of the ~12VDC that is coming into the board.  That is the larger trace that some in on the right side of the isolated plane.  How should I handle that?  Another ferrite bead?  Does that affect the voltage?

Thanks!

[Christe4nM]

For DC you can just put it trough a ferrite: one way to look at a ferrite bead is as it being a frequency dependent resistor. At very low frequencies, and DC its resistance is very low, usually a few hundreds of millohm. That still means a tiny bit of voltage drop when current goes through, but that's an issue only for precision applications. When frequency gets higher the ferrite's impedance (resistance and inductance) goes up. Most ferrites are spec'd for their resistance at 100 MHz. Frequency content from roughly 1-1000 MHz sees a large resistance in its path, and a voltage gets dropped across the ferrite instead of the load. That's what you want when you use ferrites, as this effectively removes that higher frequency content at the load side.

If it were a non-DC signal I'd have to look it up how one would handle that going into an isolated area. My best guess would be that at least a certain amount of filtering would be required to remove any unwanted (high frequency) noise. In addition a path for the return current must be provided, so directly next to the signal the grounds must be connected (filtered off course).

That's important for you to: it's probably a good thing to put the power and ground ferrites directly next to each other. That way you provide the return current a path right next to the incoming current. If you wanted to go all the way, put a ferrite from analog to system ground next to the 12V in. Or put all three: 3v3, 12v and gnd right next to each other with ground in the middle.

Another thing: make sure you put a (small) filter directly before your ADC inputs. You want any frequency content above 1/2 the sampling rate removed. (if you need to know more Google for anti-aliasing filter + ADC). Be aware that even though you measure a DC signal, it's how fast it needs to change from one level to another that determines how wide/narrow the filter can be, and how fast you need to sample at minimum.

[EK701]

Thank you, that really helps!  I'll work on an updated layout over the next few days.

Eric

[EK701]

OK, I think I implemented all your suggestions.  New PCB layouts attached.  Any new feedback is appreciated.  EDIT - updated images.

[Christe4nM]

Well I gotta admit: my first thought was "wow". You went from a good start to a really good looking layout. I hope you put them next to each other as well: the slight changes you made in routing make your current layout look quite a bit neater to my eyes. That gives any viewer already the idea that you've taken care in your design. Some go as far as to say "if it looks good, it probably is good." I cannot see anything that's wrong. If I have to say one thing its that you might've gone overboard a bit on the via stitching. But at OSHpark you don't pay for the amount of holes (equals time in the drill) required, so that's not a problem.

If you were me (since I don't know how it would be for me to be you ); just get it made, and go on to finding out if it works or not. For me that's always I bit of a scary step: like "did I really think it through, didn't I overlook anything etc." But at one point you have to say: I think I did the best I know; lets find out.

It's a shame though that no other forum members tuned in, but I guess that's because this section is relative quiet. Maybe it would help if you put the next one in "projects, designs and technical stuff" to get more views. You could always ask moderator to move this one there too.

[EK701]

Thanks for the feedback!  This is only the second PCB I've designed, but I really tried to research things as much as I could.  I kind of figured I went overboard on the stitching, but as you know, OSHPark doesn't charge extra for the holes, so what the heck!  I guess I'll get some made and try it!  I just need to finish my reflow oven while I wait for the boards.  Thanks again!

Eric

[marshallh]

Pretty good for a second pcb. You addressed everything well

[EK701]

Pretty good for a second pcb. You addressed everything well

Thank you!  Boards and stencil are ordered and reflow oven is almost done.  Hopefully I'll have some boards assembled by the first of the year.