routing ethernet and the PHY

[Gibson486]

I am routing my first ethernet board. I founds lots of guidelines online (although some conflicting, so I need to tread carefully). One thing I cannot seem to find are guidelines for the PHY to the micro. I looked at a design from ST micro with their Nucleo board for guidance. Oh my....from the PHY to the micro, they seem to just route to get there how ever possible. Does this mean that there are no guidelines from the PHY to the micro? Isn't it still a high frequency signal on the TX(0,1) and RX(0,1) lines? Are there no guidelines from the Micro to the PHY?

[Gibson486]

I am gonna guess that this something I should know? or there really is a lack of documentation? or I just need to find out the hard way?

[AndyC_772]

I'm assuming that the interface you're routing is RMII.

If so, then it's designed with good timing margins, which mean there are no specific requirements for length matching. You can tell this by looking at the data sheet for the PHY and having a careful look at the setup and hold requirements; IIRC the active clock edges are in the centre of the guaranteed window where data will be valid, so they can move around a bit without causing a problem.

You need to follow general high speed layout rules, of course, but they're not specific to RMII.

Gigabit Ethernet is a different issue altogether. If you're routing GMII (or another Gbit interface), then you definitely do need to consider the contribution from the PCB when you do your static timing analysis.

[Gibson486]

I'm assuming that the interface you're routing is RMII.

If so, then it's designed with good timing margins, which mean there are no specific requirements for length matching. You can tell this by looking at the data sheet for the PHY and having a careful look at the setup and hold requirements; IIRC the active clock edges are in the centre of the guaranteed window where data will be valid, so they can move around a bit without causing a problem.

You need to follow general high speed layout rules, of course, but they're not specific to RMII.

Gigabit Ethernet is a different issue altogether. If you're routing GMII (or another Gbit interface), then you definitely do need to consider the contribution from the PCB when you do your static timing analysis.

Thanks. RMII is correct. I had no idea what the stuff meant on the datasheet, but now I do. But yeah, I thought I needed to adhere to high speed design rules, which is why I was surprised by ST's demo board.

[bson]

RMII is only 50MHz.  It's not particularly sensitive.  The PHY to magnetics is 35MHz for 100M, also not particularly demanding.  It's pretty much connect the dots and done.

[tszaboo]

I've  run RMII though a DIN 41612 connector, and it didn't seem to mind it. It is just a fancy multi-bit SPI . Though keep in mind, that something functional doesn't mean that it will go thorough any EMC compliance measurements. The design I made didn't need to do that.