Tanner EDA -- any good?

[blueskull]

The title says it all. I was recently given an acceptable quote on Tanner, as I want to get my hands dirty on IC design. Since I believe the price is not open, I will not give the exact number. It's between $10k and $20k, including schematic capture, simulation, Verilog-A and layout editor. There's no digital/AMS stuff included, nor LVS or other verification tools.

So far, I've painfully used ElectricVLSI+Yosys+ABC, and I probably will still use this suite for small scale digital design, but the lack of simulation capability makes me crazy, especially for analog designs. As we know, many PDKs are using PSpice model or HSpice model, which can't be read by LTSpice and NGSpice, so I can't run simulations with PDK models.

Most of my planned designs are pure analog or power with little digital that can either be laid out by hand, or can be generated with Electric+Yosys+ABC and being exported as GDSII macro block. I don't do fancy 2-digit-nm digital designs. Most of the so called digital parts are SERDES, 8b/10b, SPI, I2C and similar communication stuff plus some simple logic.

Tanner T-Spice claims to read PSpice models and HSpice models, and it seems many legacy processes (180/250/350/500/700) are available in native Tanner PDK format, so that makes my life a little bit easier.

I want to ask for your opinion -- is Tanner any good? Is there any other options for entry level analog-dominant IC design?