Trace Width consideration for DirectFET

[felixnavid]

My application: I'm building a H-Bridge for Brushed DC motor, that can handle a peak of 70A for a couple of seconds.
I have found the AUIRF7736M2 mosfet in a DirectFET M4 package. The transistor can handle my requirement with ease, the continuous MSOA peaking at 102A.
The problem is with the package, the M4's total width is 6.25mm and in that space I have to squeeze the source trace, the gate trace and the edge of the drain pad.
I'm left with a trace of around 4mm for the source. On a 2oz/ft^2 board, if I let the trace heat up 60°C over ambient I might be able to pass 25A. Nowhere near the transistors ability to handle 100A DC.
On other packages, like D2PAK I'm able to solder wires on top of the trace so that it can handle more current, but with DirectFET I have an area covered by the transistor itself where I can not add any wires.
Am I missing something or this transistor was not designed to be put on a "normal" PCB? I really like how well tested and documented these transistors are and would not like to switch to something else.
https://www.infineon.com/dgdl/auirf7736m2.pdf?fileId=5546d462533600a4015355adac5913fb

[DerekG]

Add multiple vias into the tracks that leave the source.

Advice: Add 0.3mm vias, 0.8mm apart. Have the board manufacturer plate the vias shut (fully closed).

[T3sl4co1l]

Two things:
1. Use a multilayer board with lots of vias.  This greatly increases the copper cross section available (and can reduce stray inductance, also a priority at these low impedances!).
2. Trace width is only a meaningful restriction over long distances (say, L/W > 5).  Over short distances, the current density is going to be higher anyway (current has to neck down to the pad), so you can't really save anything anyway.  More importantly, you're going to have a heatsink and thermal pad clamped against the thing, which sinks heat out of the devices and traces, so you can tolerate far higher power density in the traces.

You can also simply order 3 or 4 ounce boards, they're not scary expensive.

Tim

[PCB.Wiz]

The problem is with the package, the M4's total width is 6.25mm and in that space I have to squeeze the source trace, the gate trace and the edge of the drain pad.
I'm left with a trace of around 4mm for the source. On a 2oz/ft^2 board, if I let the trace heat up 60°C over ambient I might be able to pass 25A. Nowhere near the transistors ability to handle 100A DC.

You can run the source trace both ways, and also use copper pour areas for maximum useful width, if that is still not enough, there are  via-arrays and multiple PCB layers to consider using...

Note that 100A you mention, generates 30 watts in the 3mOhms, which will be a challenge to manage!.
Even 70A is ~ 15W, still well above PCB mounted alone.

My application: I'm building a H-Bridge for Brushed DC motor, that can handle a peak of 70A for a couple of seconds.

You might want to get more exact numbers on the actual current profile - very short inrush current, can use the thermal inertia in all the head-sink paths.

[felixnavid]

I'm using home made PCBs for a single prototype (I can't wait 1 month for my boards to arrive), later using a manufacturer. My vias will be filled with wires and solder. According to a calculator (http://circuitcalculator.com/wordpress/2006/03/12/pcb-via-calculator/ ) a 0.8mm completely filled via can handle 36A. I can fit 3 columns of them with 0.5mm distance between them, maybe 3 in a row (under the transistor) or even more next to the transistor. Would this be enough? Regarding the high Rdson, a better transistor in this regard would be more expensive (in this package, for this prototype), so I'm thinking or puting 2 of my 3mOhm mosfets in parallel.

[DerekG]

My vias will be filled with wires and solder.

Excellent idea.

so I'm thinking or putting 2 of my 3mOhm mosfets in parallel.

In your original post you mention 70A for a couple of seconds. If this is how you are using them, then a big heatsink (or a second mosfet) may not be of great value to you as you will be turning them off before the silicon junction & the heatsink get much heat in them.

Of course, if you are turning them on again every few seconds you may need the heatsink.

Mosfets (normally) share the load by increasing their internal resistance as their temperature rises. If you are not getting their silicon junctions fairly hot, you will find that one mosfet only will be doing all/most of the work.

[felixnavid]

On a 2 layer board with a trace on both sides with a enough vias connected between them, if my source (mosfet) and sink (cable connector) are on the same layer, will current flow through the second layer? Considering that electrons travel on the edge of the trace that seems true, but I'm not sure.
DirectFET package has the advantage that the junction is placed right under the metal package so thermally I sould be able to mount a solid heatsink ( no cuts) so that I get decent thermal capacitance.

[DerekG]

Considering that electrons travel on the edge of the trace that seems true, but I'm not sure.

Electrons take the easiest path & that path has the lowest resistance.

Normally this means that the majority of the electrons will travel along the track that is at the lowest temperature. As this track's temperature rises, the electrons will search out another cooler track.

[T3sl4co1l]

Considering that electrons travel on the edge of the trace that seems true, but I'm not sure.

Electrons take the easiest path & that path has the lowest resistance.

Normally this means that the majority of the electrons will travel along the track that is at the lowest temperature. As this track's temperature rises, the electrons will search out another cooler track.

Please cease and desist from repeating this silly old saw.  It's confused so many beginners, while giving no actual insight!

Electrons most certainly do not clump together into a tiny filament along the one tiny slightly-lower-resistance path.

Charges (not just electrons!) follow each possible path, inversely proportional to the resistance of each path.

Nothing more, nothing less.

At AC, the path of least impedance is along the surface and edges of conductors (skin effect), which is still not to say that current goes to zero inside a conductor (except at certain locations, because of some neat physics), just that that's not where the majority is flowing.

For a switching transistor, current is an about equal superposition of DC and AC, so one must consider both.  Keeping the path short to reduce inductance, is equivalent to keeping the path of least impedance spread out widely, so it's a doubly good goal.

Tim

[DerekG]

At AC, the path of least impedance is along the surface and edges of conductors (skin effect)

The original poster said he was switching on the transistor for "a couple of seconds" ............. so not much AC present here!

[T3sl4co1l]

At AC, the path of least impedance is along the surface and edges of conductors (skin effect)

The original poster said he was switching on the transistor for "a couple of seconds" ............. so not much AC present here!

I assume he's controlling it, not just slamming it on and off, and that that's the maximum load.

Tim