Why is the footprint of the thermal pad so small on this IC?

[ocset]

Hello
The 25th page of the below app note shows the land pattern of an offline linear LED driver IC.
The FETs in this package operate in the linear region.

  Why is the land pattern showing a central thermal pad of dimension just 3mm by 3mm?
There is room there to make it 4mm by 4mm and still have plenty of clearance away from the actual outer pads. The solder mask could still be 3mm by 3mm so that the IC “locates” in the centre of the land pattern during the reflow soldering process.
So why have the manufacturers not recommended a bigger thermal pad for this IC?

DT3001 LED driver IC:
http://www.seoulsemicon.com/_upload/Goods_Spec/Acrich2-Applicationnote.pdf
 

[T3sl4co1l]

Uh, the thermal pad is just where there's metal on the package to make a solder joint... you can put whatever around it (or vias in it).

Tim

[ocset]

Thanks,  the Seoul app note didnt say that the 1mm of clearance from centre thermal pad to outer pads was due to insulation reasons, -but i appreciate you could be right. Apparently the thermal pad is not connected to any of the  outer pads.

Our PCB layout engineer has placed five thermal vias of diameter 0.65mm in the thermal pad of our DT3001 IC. (as in the jpeg attached).
he seems to have just used five square PTH vias, which as you can see , dont fit together very well and hence there is solder resist between them. Is this bad?
So he has got solder resist over the thermal pad. (as attached)
Surely 0.65mm is way too big for a thermal via in such a small thermal pad?
(he has made the thermal pad 3mm x 3mm)

[T3sl4co1l]

It doesn't look like he made a pad for the thermal pad at all.

There should be a separate pad object, with copper and soldermask opening, in the middle.

Tim

[floobydust]

It's a power IC so you don't want to mess this up.
Good thermal design app note from Cree for XLamp LEDs.
They compare via size+spacing, #vias, solder-filled or not etc.

I would use smaller vias, more of them, and a dedicated full-size thermal pad with no breaks.

[Kjelt]

Thanks a good document.
I experienced the hard way, thermal vias were open and during the reflow the solderpaste was absorbed by the via leaving airgaps in the thermal pad connection resulting in early dead of my power led driver.
So fill them before or close them or expand the thermal pad copper outside the ic pad and stitch them there with thermal vias.

[T3sl4co1l]

Via-in-pad is best done with small vias (< 0.3 mm ID), which don't wick solder very much (particularly lead-free, which flows more slowly than leaded).

Soldermask tenting isn't recommended because of the added height under the component (the thermal pad will rest on top of the soldermask), and the significant reduction in contact area (you've basically made a via-tent sized void in the solder joint).

Alternately, if you have a wave soldering step, you can possibly recover the pad solder by using large vias (>= 0.5 mm) and leaving them fully open.  Wave solder wicks up and fills the vias and pad area.  Or traps bubbles in the vias, because they're not open and vented at that point. Whatever.

If you can afford a custom PCB fab, filled and capped vias are wonderful.  They are plugged with epoxy, leveled, and plated over with copper.  The resulting surface is smooth and planar, without voids (maybe a perceptible dimple where the filler is, that's all).

Tim

[bson]

I don't see any suggested land patterns in that document.  You must be confusing the package drawing with a land pattern.

[DerekG]

Via-in-pad is best done with small vias (< 0.3 mm ID), which don't wick solder very much (particularly lead-free, which flows more slowly than leaded).

Correct. If running production quantities, you can often organise with the board shop to plate the 0.25mm/0.3mm vias completely shut. This is by far the best option. Many board shops don't charge extra for drilling 0.3mm holes, but they do charge extra for anything smaller than this.

Soldermask tenting isn't recommended because of the added height under the component (the thermal pad will rest on top of the soldermask), and the significant reduction in contact area (you've basically made a via-tent sized void in the solder joint).

Quite correct.

Alternately, if you have a wave soldering step, you can possibly recover the pad solder by using large vias (>= 0.5 mm) and leaving them fully open.  Wave solder wicks up and fills the vias and pad area.  Or traps bubbles in the vias, because they're not open and vented at that point.

We have found this to be unsuccessful (it even affects 0.3mm holes to some degree if they are not plated shut). When the solder wave "leaves" the pad, capillary action often sucks the solder from the top side of the board away from the SMD heatsink. This leaves a poor thermal connection between the top side copper and the underside heatsink of the SMD component. We were having a few failures & so organised x-rays to tell us what was going on.

For the above production boards, the bottom side holes were taped over before wave soldering to prevent the capillary action sucking the top side solder down the holes.

[T3sl4co1l]

Hmm, accidentally sucking the solder out the back side, I'll remember that!

Tim

[pcbguy1927]

Here is an article on an new alternative using QFNs with open thermal via-in-pad (VIP) structures reduces cost and eliminates solder wicking as recommend by IBM and endorsed by PCB Libraries.

http://pcdandf.com/pcdesign/index.php/magazine/10676-btc-design-1603
https://www.pcblibraries.com/forum/ipc7093a-btc-qfn-solder-mask-defined-thermal-pad_topic2154.html

[ocset]

Thanks, PCBGuy1927 your articles are fantastic!
I see that they never recomend thermal vias as big as 0.65mm diameter as our PCB  contractor uses........do you know, is there ever a situation where a thermal via in a pad would be as big as 0.65mm diamater?