Solartron 7071 / 7081 last digit is jumping all over the place

[e61_phil]

Hi,

today I got my Solartron 7071. After a quick check of the meter I removed the LK17 jumper to get an 7081.
I thought it is a great upgrade of my HP 3456A and a relatively cheap entry in the world of 8,5 digits.

I connected the meter to different sources (Knick JS3010, Fluke 343A and a LTZ1000) and regardless of the source the last digit is jumping all over the place. That means in 5,5 digit mode it is only a usefull 4,5 digit meter, in 6,5 a 5,5 and so on... At the same time my 3456A was connected and the reading was stable to 6,5 digits even with only 10NPLC.

The meter itself seems to be stable. In 8,5 digit mode measurements against my sources are all well below 0.5ppm over an hour. It seems to me like a noise ADC.

Is this a normal behavior of this unit? So, I think without removing the jumper to get a 7081 there is no benefit to my HP 3456A.

Philipp

[Andreas]

Hello,

according to test spec at 10V input the rms noise should be below 3uV RMS for 10 successive readings.
(or 20 uVpp).
http://www.perdrix.co.uk/Solartron7081/Solartron_7081_Test_Spec.pdf

with best regards

Andreas

[ManateeMafia]

Congratulations on your new gear. Check the usuals... power supplies. Also, some of those had the Varta battery. I have seen a couple of leakage issues that went all over. Some went down the plastic standoffs and created a path for the power supply rails. Also, it can get under parts that look fine but are eating away at the traces. No cals are lost with the battery, but it can make it boot/hang with errors.

[e61_phil]

I did some further measurements with my HP 3456A in parallel.

The Solartron was set to 6,5 Digit Mode and the HP 3456A was also set to 6,5 digits and 10 NPLC. So, both meters deliver a new value every ~400ms.

To be sure there is no problem with cable EMF or something like that, I shorted the cable directly on the calibrator (Fluke 343A was used). The measured peak-peak value was about 600nV on the Solartron and a bit higher on the HP 3456 (much cheaper cables were used) (short.PNG). Everything was well below 10µV so I shouldn't care about it in the 10V range with 6,5 digits.

The next measurement was 10V from the Fluke 343A. The HP 3456A showed a very stable measurement with only a few times one last significant digit up (1ppm peak-peak). Unfortunately, the Solartron showed 14ppm peak-peak and 1,3 ppm rms (10V.PNG).

I can't believe that this should be ok for this meter. Is that really the case??

[Andy Watson]

Are you running it as a 7071 or a 7081? And does it make a difference to the last digit?

[e61_phil]

I'm running it as a 7081. I don't know if it makes a difference. I will have a try tomorrow.

[e61_phil]

In 7071 mode, there is no difference in the measurement.

[acbern]

I have a 7071 (not modified to 7081), and this is certainly not ok, provided the source is stable (as seems to be the case here).

[e61_phil]

I have a 7071 (not modified to 7081), and this is certainly not ok, provided the source is stable (as seems to be the case here).

Do you have any measurement over a few minutes with a stable source in 6,5 digit mode?


If one activate the digital filter with a walking window it looks fine. So it is really noise and not an instability, I think

[e61_phil]

With the gliding average window (aka digital filter) switched on everything looks much better. The attached measurement was done in 7,5 digit mode and the 3456A set to 100NPLC. The measurement shows the warmup of the Fluke 343A (which makes some problems now, but that is another story..). I added some offset to one of the meters to align the curves.

[Mickle T.]

With the gliding average window (aka digital filter) switched on everything looks much better. The attached measurement was done in 7,5 digit mode and the 3456A set to 100NPLC. The measurement shows the warmup of the Fluke 343A (which makes some problems now, but that is another story..). I added some offset to one of the meters to align the curves.

I think this 7081 have a problem with a PLL to mains synchronization. Look at the "9.8 Analogue checks" of the Solartron 7081 Maintenance Manual to adjust the PLL frequency.

[e61_phil]

@DigilentMinds.com it is a doom-loop

I think this 7081 have a problem with a PLL to mains synchronization. Look at the "9.8 Analogue checks" of the Solartron 7081 Maintenance Manual to adjust the PLL frequency.

To not destroy anything: Is it right to disconnect the power cord from the 7081 and only supply 2.5V from an external power supply Between TP904 (-15V) and the low side of C806?

I'm a little bit confused about: "monitor the voltage at the negative end of C806 with respect to TP904. The voltage should settle to 2.5V +/- 0.3. Adjust C807 to correct if necessary."

If I supply 2.5V why should I measure it? And how can C807 adjust my external power supply?

And do you know if 5.21MHz to 5.27MHz is also the right frequency for 50Hz?

The next step is: "Disconnect the bench supply and switch on the 7081 using 60Hz mains frequency. Check that, after settling, the voltage on C807 is 2.5V +/-0.5V." Know I should measure von C807?

Thx
Philipp

[e61_phil]

My first measurement with line cord connected on Pin5 of the IC835 shows 5.24 MHz is it ok for 50Hz or should it be 4.36 MHz?

[Mickle T.]

1. 7081 must be connected to the mains, switched on and preheated during >15 minutes.
2. PLL in the steady state must have a 5.2428 MHz output frequency (at any 50 or 60 Hz mains frequency) and 2.5 V on the input (C806). If not, slowly adjust C807 to correct it. Absolutely no any external supply needed!
 

[e61_phil]

1. 7081 must be connected to the mains, switched on and preheated during >15 minutes.
2. PLL in the steady state must have a 5.2428 MHz output frequency (at any 50 or 60 Hz mains frequency) and 2.5 V on the input (C806). If not, slowly adjust C807 to correct it. Absolutely no any external supply needed!

Thx

I've attached the measurement between TP904 and C806. It seems to be a bit low, but within the +/- .5V tolerance.

If I adjust C807, I think it will change both frequency and voltage. Is it right, to have a look on the frequency to adjust C807 and not on this 2.5V?

[Mickle T.]

I think it's all Ok. No adjustment needed.
The next of the possible problems is a zener 

[e61_phil]

I think it's all Ok. No adjustment needed.
The next of the possible problems is a zener 

To late I adjusted it a bit more to 2.5V but you're right: no change in the reading noise


I am reassured that it does not seem to be normal with the reading noise. I've read in your documentation pack: 6µVpp in 7,5 digit mode and 4µVpp in 8,5 digit mode. Even 6µVpp in 7,5 digit mode can cause the last two digits to jump. If the noise increases in 6,5 digit mode I thought it can be normal for the meter (which I think is very bad).

What is your meaning on the measurement noise I showed here?

[Mickle T.]

It's a difficult question. The most silent of my 3x Solartron 7081 has a zero noise on the 6.5-digits 10 V mode with 10 V reference connected. The most noisy has a 2-3 ppm jumps. (without any moddings, of course)

[Kleinstein]

The significant higher noise for the 10 V measurement compared to the short circuit measurement is suspicious. It points to a problem with the reference voltage or possibly leakage at the input protection if the 10 V are to close the the limits.

It might help to do a test at 5 V as well (to exclude beginnging leakage) - noise from the reference would be half, leakage from getting close to onset of limiting should be much lower.

Another test would be measuring resistance - here reference noise should cancel out, but still using the ADC at high values. So if readings are more stable this would point to a bad reference.

One could test the line frequency suppression by measuring the DC volts from a pure AC voltage (e.g. about 5 V AC (line synchronous) in 10 V DC range) - a bad PLL lock would result in a low difference frequency. Adjustments at the PLL should not chance much on the lock, so it would mainly change the lock range and maybe the speed to get a lock, but hardly the final readings once the PLL is locked. With the PLL control voltage not at it's limits the PLL is very likely locked.

[e61_phil]

I measured the input current earlier today and it was about 8pA on a 10V input. (100G in series to the input will cause 800mV of drop)

Is it possible to have a very noise but stable reference? A measurement on the LTZ1000 in 8,5 digit mode and digital filter on was stable to below .4ppm over a few hours.

I will do some measurements with 5V. For ohms measurement I have to install a second pair of binding posts first.

Thanks for your great help!

[e61_phil]

I had a short try with 5V and it gives also 14ppm peak-peak.

Now, I set both meters in manual range 10V and short the cable at the calibrator. In this setup the Solartron is measuring 110µV peak-peak


I think it is a problem with the ADC. I tested the manual ranges 1V, 10V, 100V and 1000V and the noise is in every range around 10 counts.

Edit: The maintenance manual stated, that this could be the chopper amp (IC201 ICL 7650).

[Mickle T.]

Shorting the DMM's cable isn't enough to check ADC noise. 7081 have a special test mode to do this: type "mode,test0" in the RS232 terminal.

[e61_phil]

Shorting the DMM's cable isn't enough to check ADC noise. 7081 have a special test mode to do this: type "mode,test0" in the RS232 terminal.

I've connected the Solartron via GPIB, but I think that doesn't matter.

In TEST0 mode there is also these around 10 count noise (see attachment).

[e61_phil]

I replaced IC201 (ICL 7650 chopper amp) but that doesn't help

[Mickle T.]

The next thing is a power supply (+15, -15 and 5 V).

[e61_phil]

The next thing is a power supply (+15, -15 and 5 V).

The power suppy was the first thing I have checked. There was no 50Hz Ripple. The noise was about 100mVpp.

[TheSteve]

The next thing is a power supply (+15, -15 and 5 V).

The power suppy was the first thing I have checked. There was no 50Hz Ripple. The noise was about 100mVpp.

Seems like an awful lots of ripple for the power supply in a precision instrument. 

[Mickle T.]

7081 Floating Power Supply noise, measured by HP 34401A.

[e61_phil]

7081 Floating Power Supply noise, measured by HP 34401A.

Thank you soo much A comparison is extremly helpfull!

It seems, that TheSteve is right.

This time I measured the Rails with my HP 3456A to compare it with Mickles values. Most of the voltage are extremly close to Mickles, but TP901 to TP903 has 0.8mV (I think that could be ok) and the noise of the +/-15V rails is about 10times higher than Mickles.

My next step is to replace all caps with new ones in the floating power supply.

[e61_phil]

I replaced C903 and C904, but that doesn't change anything.

I read this http://www.gellerlabs.com/34401a%20ac%20zero.htm

Perhaps the measurements of the 3456A and the 34401A aren't comparable in the sub mV rms range? I had another look with the scope and it looks quite well. I think the power supply is ok.

Another thing I wonder about is the -20µV Offset in Test0 mode. This offset stays in 6.5, 7.5 and 8.5 digit mode. Is an offset in Test0 mode normal?

[Mickle T.]

Some µV Offset in Test0 mode is absolutely normal. My 7081#2 have even more offset in "Drift,off" mode.

[e61_phil]

Ok..

I think your graphic was measured in 8.5 digit mode. Do you have any measurements in 6.5 or 7.5 digit mode?

I've attached another Test0 measurement in 7.5 digit mode. It shows 11µV peak to peak within a few minutes

I think in 8.5 digit mode it is hard to see if there is also this around 10 count noise, because there will be real zero noise in the last digits.

[Mickle T.]

I have only 7.5-digits mode TEST0 statictic.

[e61_phil]

I did some further measurements..

I fed in a stable voltage and measured the signal path down to the ADC. All outputs (Input Amplifier and DC Ranging) are stable (measured with 3456A and scope). Therefore, I'm sure there is no power supply issue. The reference voltages are also completly stable measured with the 3456A.

Next step was to desolder SP501 (the voltage at this point was also stable before desoldering) and feeding a stable voltage directly into the ADC. This results was the same jumping display as seen before.

Now, I'm completely sure that the ADC is the problem. I already replaced IC201 with a new one. I think it will be hard to track down the error in the last digits. On the scope everything looks fine of course.

Any ideas?

[ManateeMafia]

What about the +/- 10v references at TP302 & TP303?

[e61_phil]

What about the +/- 10v references at TP302 & TP303?

Absolute stable on the 3456A.

[ManateeMafia]

I had a Keithley 2001 failing ADC diagnostics due to a leaky FET that I was able to compare to others on the same board. I am pretty sure it was the ADC noise test.

Unfortunately, the VN67AK and 3N163 are not cheap.

[e61_phil]

If only one FET is damaged, the DMM should be stable in the other input polarity or not?

[ManateeMafia]

Good question. I cannot answer that, but it looks like both + and - references are always used as part of the forcing waveform. I am sure someone here can give a better answer.

BTW, I have a couple of the 7081 and have been following your progress. These are nice voltmeters and it is a good complement to the 3456A.

[e61_phil]

Yes, you're right. Changing the polarity doesn't make any difference . TP204 is switching between both rails, as you mentioned.

To get the VN67AK seems to be quite difficult. The 3N163 costs about 20$ at farnell, but one can buy it.



It seems to me, that there are a lot of 7081 around .

[ManateeMafia]

You can get them from here

http://www.americanmicrosemi.com/products/search/index.php

I have never used them so I don't know if they are trustworthy. Most seem to use random number generators for inventory levels. At least they do have pricing and accept PayPal so there should be some protection.

[e61_phil]

You can get them from here

http://www.americanmicrosemi.com/products/search/index.php

I have never used them so I don't know if they are trustworthy. Most seem to use random number generators for inventory levels. At least they do have pricing and accept PayPal so there should be some protection.

Thx

I there a way to measure these transistors before I spend 100€ for nothing? (shipping to germany is expensive)

Do you know why they use these 3N163 with only 20fA input current? The gate drive is low impedance anyway.

[TiN]

As with any integrating ADC, +/- reference with related switched resistors are used to provide current for ramp-up/ramp-down steps, so current in ADC is more important than voltage, but it's bit PITA to measure properly.

One thing I can suggest - try relocating 7081 somewhere else in the lab, it could be pickup of some EMI from something nearby. Sounds vague, but you never know.

[Mickle T.]

For testing purposes you can swap VN67 and 3N163 from Ratio Circuit TR505,506 and Ohms Circuit TR603,610.
The oldest revision of 7081 have a VN10 instead of VN67 in the ADC, the latest - WM222. Also R222 can be adjusted to set TR201/202 ~30 uS dead time.

[e61_phil]

I swapped the four transistors, but nothing changed

(2x 1N163 and 2x WM222 from ratio and ohms)

Later I will have a closer look at the deadtime. There was a deadtime on every edge, but I havn't measured it. Therefore, I don't think deadtime is the problem.

[e61_phil]

Deadtime is around 38µs. With a discrete Jitter (much smaller than the 38µs)

[Kleinstein]

Visible jitter at the dead time could be a problem. The jitter would be part of the PWM signal, thus even 0.1 µs jitter could give noise in the ppm level range.

[e61_phil]

I've attached a measurement of the deadtime jitter. Signal was measured on TP204 (GLUGS)

[Kleinstein]

This dead time is the time when essentially no current flows from the reference. The jitter looks like just steps of the ADC clock (seems to be 5 MHz). So it does not look critical, it's about what I expect: mainly one of two values with what looks like a single event of one more off. So far the switching looks OK.

If in a socket, one could try replacing U202 (LM301), as noise from this OP also enters ADC performance.

I would also consider adding local decoupling at the supply of OP IC201 - at least the plan I found does not have it (may be a note somewhere ?), which is a little strange.

[e61_phil]

This dead time is the time when essentially no current flows from the reference. The jitter looks like just steps of the ADC clock (seems to be 5 MHz). So it does not look critical, it's about what I expect: mainly one of two values with what looks like a single event of one more off. So far the switching looks OK.

If in a socket, one could try replacing U202 (LM301), as noise from this OP also enters ADC performance.

I would also consider adding local decoupling at the supply of OP IC201 - at least the plan I found does not have it (may be a note somewhere ?), which is a little strange.

Ok, I didn't save this picture the first time, because I also thought it should be ok. After your post in you said 100ns could be crucial I saved a picture. Ok, PWM is also fine..

I already installed a 100nF ceramics and a 2.2µF MKS on IC201, that doesn't changed anything.


There ist not much left. IC202 isn't in a socket, but if I found a LM301 in my lab I will replace it. Perhaps I should also try to replace the comparators (IC203 and IC204).


Might it be the case that a leaky integration capacitor cause this problems? I saw a huge offset an much more noise after cleaning the FET soldering, since some IPA went under IC201. It vanished after drying with a hair dryer.

[Mickle T.]

There is another part of ADC: forcing waveforms switch IC307.

[picburner]

In my 7081, as well as other failures, I also found a leaky C201 (100nF 200V 1%) which gave me a random  instability on the latest digits.
Measured with a multimeter it looked good but it was leaky under a more high voltage.
The replacement, in my case, has solved the defect.

[e61_phil]

In my 7081, as well as other failures, I also found a leaky C201 (100nF 200V 1%) which gave me a random  instability on the latest digits.
Measured with a multimeter it looked good but it was leaky under a more high voltage.
The replacement, in my case, has solved the defect.

That sound interesting! What kind of capacitor do you use as a replacement?
I have some 100nF MKS caps here. Might they work?

There is another part of ADC: forcing waveforms switch IC307.

Ah, ok it looks like another switching between the references. I will have a look with the scope.

[Kleinstein]

C201 is the main integrating capacitor. So it should be low loss for highest accuracy / linearity. So MKS might be Ok for a first test, but the proper type would be MKP or similar.

The trouble could be not only leakage, but also increased loss due to humidity / delamination.

[e61_phil]

I replaced C201 with a 100nF 63V MKS (a fraction in size of the original C201) and the noise is still the same. Perhaps, this very small MKS is a bad replacement or there is another problem.

I had a brief look at IC307 and it looks ok. I will check jitter later.

[Kleinstein]

A MKS cap might be just as bad as an MKP that got to much humidity inside. So I would keep that capacitor in mind. A new MKP type might be quite large, as 200 V types are not that common.

Doing a few noise tests at different integration times might also help and give a clue.

[e61_phil]

Doing a few noise tests at different integration times might also help and give a clue.

I made some tests with different number of digits. It seems to be in every mode the last digit is noisy. Or is there another way to change the integration time?


IC202 has now a socket with a new LM301 installed. But still nothing changes..

Is it normal that one can see the GLUG switching at many places? Perhaps the caps around IC205 are gone bad? I will have a look at C213 (47µF).

[Mickle T.]

Is it absolutely normal that you can see the GLUG switching at many places. The input amplifier MDM channel and ADC are fully synchronous, so there is no problem.

[wiss]

Is IC404 stable?

[e61_phil]

Is it absolutely normal that you can see the GLUG switching at many places. The input amplifier MDM channel and ADC are fully synchronous, so there is no problem.

Yes, a 22µF in parallel to C213 didn't changed anything. As you mentioned.

Is IC404 stable?

I haven't measured IC404 directly but the whole chain from the input jacks to the ADC input (measured with HP 3456A on R201) seems to be stable. And I opened SP501 and injected a signal directly into the ADC. That was also noisy.

[Kleinstein]

The testpoint TP202 / TP203 might be interesting to see if switching of the FETs is really working as supposed.

Another option for fault finding might be using hot or cold air to test components / circuit parts. Faulty parts may be more sensitive to temperature / tapping.

The caps at U205 are just part of the digital supply - one could check the noise at the supply to see if there is to much noise there.

If all is working perfectly, I would expect one main noise source to be the LM301 of the integrator. Low frequency voltage noise is set by the chopper OP, but current noise of the OP should be significant for all frequencies, and the 100 K resistors at the input are rather high impedance. Though a long shot, it might be worth a try to do a upgrade with this OP to a low noise JFET based OP, like OPA134 or OPA140. Pin 1 would be left open, as these OPs are internally compensated.

[e61_phil]

The testpoint TP202 / TP203 might be interesting to see if switching of the FETs is really working as supposed.

Ok, anything I should have a closer look on? The damn thing with this meter is: It works except these noisy last digits. So it is very hard to see any fault with the scope.

Another option for fault finding might be using hot or cold air to test components / circuit parts. Faulty parts may be more sensitive to temperature / tapping.

I've tried that already with coolant spray (or whatever "Kältespray" in english is..) but it is very difficult to see anything. Every time the offset increases, in cause of ice out of the air humindity and this ice will melt and leave water on the pcb. Unfortunately, I have no equipment to apply hot air on a small region.

If all is working perfectly, I would expect one main noise source to be the LM301 of the integrator. Low frequency voltage noise is set by the chopper OP, but current noise of the OP should be significant for all frequencies, and the 100 K resistors at the input are rather high impedance. Though a long shot, it might be worth a try to do a upgrade with this OP to a low noise JFET based OP, like OPA134 or OPA140. Pin 1 would be left open, as these OPs are internally compensated.

I'll keep this in mind . I think there is much room for improvements as Mickle showed. My favorit opamp for low noise, low input current stuff with some GBW is the ADA4817 (haven't checked the specs against your candidates for this application)

[e61_phil]

Some further measurements...

I had a closer look to the forcing waveform. I've measured between C212 and R221 (yellow) and Pin 9 of IC833 (blue). Or rephrased: Blue is the driving signal of IC307 and yellow is the AC coupled output.

The falling edge looks fine but the rising edge showed some jitter. The jitter seems to be around 50ns. Could that cause my problems?

I think the jitter is too small to cause the problems. Periodtime of 160Hz ist 6.25ms. And 50ns is only 8ppm of 6.25ms. And one 6.5 digit measurement lasts 400ms. So 64 times 6.25ms. The square root of 64 is 8. This should reduce the 8ppm jitter to 1pmm, I think.


I had also a brief look at TP204 against TP203. It looks fine. No jitter at all. For measurements at TP202 I have to desolder the 22µF next to C213 first. But it is too late for soldering today

PS: Blue is 2V/Div not 20

[Kleinstein]

The forcing waveform should not show any significant jitter. It is derived from the PLL signal, so it really be stable to maybe +-5 ns. Especially if jitter is only for one slope, this is suspicious, as noise from the PLL would effect both sides. So this is definitely a point to look at. It could be either IC307 or just decoupling of that chip and less likely the driving level or ground.

Noise on the forcing waveform might have quite a big effect, as the forcing waveform is coupled rather strong to the integrator with 40 K resistance, compared to 100 K for the signal and refference.

The  ADA4817 is very good at high frequencies, but not that good at lower frequencies. It's also rather fast and might not be stable in such a circuit. The OPA140 is a JFET OP with exceptionally low noise in the LF region. So while higher noise at 100 kHz, it's much better at 100 Hz. Also the OPA140 is not that fast (still faster than LM301) and ins available in DIP.

[e61_phil]

The forcing waveform should not show any significant jitter. It is derived from the PLL signal, so it really be stable to maybe +-5 ns. Especially if jitter is only for one slope, this is suspicious, as noise from the PLL would effect both sides. So this is definitely a point to look at. It could be either IC307 or just decoupling of that chip and less likely the driving level or ground.

My measurements shows only jitter from IC307 (input -> output). The scope was triggered to the forcing waveform. Therefore, the jitter from the forcing waveform itself isn't shown. I will do some jitter measurements on the forcing waveform itself later.

Noise on the forcing waveform might have quite a big effect, as the forcing waveform is coupled rather strong to the integrator with 40 K resistance, compared to 100 K for the signal and refference.

Shouldn't it affect the measurement only relative? So x ppm Jitter should only result in x ppm noise without any relative amplification?

[Kleinstein]

The forcing part is added with a smaller resistor, so about 2,5 times (40 K vs 100 K resistance) the amplitude as a normal signal. So the +-10 V forcing signal will look like a +-25 V signal at the signal input.
So as a first approximation a 1 ppm error due to jitter in forcing waveform could have a 2.5 ppm (of full scale) on the output. It gets even a little more complicated, depending at which time the integration is ending. Also the forcing signal is AC coupled, which should reduce the effect, but occasional jitter will include components at frequencies below sampling frequency. So I would expect the noise due to this problem to go down faster than sqrt(time) with longer integration time. Still the jitter effects can show correlation over time making it difficult to estimate the error.

For only 50 ns Jitter I would also expect less noise, but who knows how the scope probe might influence the circuit.
But at least the jitter from the control input of U307 to outputs of U307 shows that there is very likely something wrong with this chip - there may be more trouble (e.g. higher resistance, charge injection) than just the jitter.

I would not expect much jitter with the controlling digital signal, but you never know. Jitter of the forcing signal should be better visible before the capacitor, as this would include less effect from the integrator part.

[e61_phil]

I've tried to measure the jitter on the forcing waveform itself. It seems to me, that there is a huge jitter. But it is next to impossible to measure, cause of the instability of the frequency (which is related to the mains 50Hz instability)

[e61_phil]

And the story goes on..

To be able to measure the jitter on the forcing waveform I cut pin 6 of IC834, which gives the line frequency. At this point I fed in stable 50Hz out of my function generator.

The jitter in periodtime on the forcing waveform is quite large with about 300ns.


Edit: I saw my Siglent SDG1025 function gen generates a lot of jitter on the 50Hz output. I swapped to my HP 8165A, which also creates some jitter but far less than the siglent. With the HP generator the jitter of the forcing waveform is reduced to approximately 100ns. With this setup the Test0 noise is nearly halfed from 11µVpp to 6µVpp. This seems to be the right way. But I thought the PLL circuit should reduce the incoming jitter quite a lot?

But what can be the problem with the mains frequency? This frequency drifts around but should have no jitter.


Edit2: I kept it running and now I'm not sure if the noisy is really improved.

[Mickle T.]

Mains 50Hz instability is a reason why I kill PLL in two of the three my 7081's.
Datron 1271 disables the PLL's voltage control input during the most sensitive phase of conversion. Datron 1281 have no PLL at all.

[e61_phil]

Mains 50Hz instability is a reason why I kill PLL in two of the three my 7081's.
Datron 1271 disables the PLL's voltage control input during the most sensitive phase of conversion. Datron 1281 have no PLL at all.

I heard about your modification. Do you create a new 60Hz signals or direct 5.24 MHz? And is it enough to feed 5.24MHz into the CLK net (pin 5 of IC835) or is it neccessary to be within phase with the signal which comes out of IC834 pin 6?

[Mickle T.]

7081(#1) have a TCXO 10485 kHz, connected to pin 3 of IC835 (trace to R816, TR807 was cuted). 7081(#2) have a programmable  silicon MEMS based CMOS oscillator 5242.8 kHz, connected to the trace from pin 5 of IC835 (pin is disconnected).

[e61_phil]

Thanks Very interesting. It would be fun to improve the meter later, but at first it should run as proposed by Solartron.

But, for further testing I will disconnect pin 5 from IC835 and feed in 5.24MHz out of a function gen. But this will drive IC824 into saturation, I think. Furthermore, the chain from mains all the way down to the 10Hz output from IC820 will stay coupled with the mains frequency (and no longer in phase with the 5.24MHz).

These long term Test0 measurements, were they done with a modified 7081 or with your third unmodded device?

[Mickle T.]

Both (modded and unmodded) shows ~ the same results in TEST0.

[Kleinstein]

Ideally the PLL will reduce the Jitter from the line frequency somewhat, at least the higher frequency part.  Still this is not easy, as it take quite long filtering times / stable VCO, which are not easy to realize.  Lots of solar power and some wind power might give additional jitter to the line frequency - so things might have worked better 20 years ago.

It is possible that the PLL is not perfectly working. This could be something like a capacitor in the PLL filter lost capacitance, or also the "sine" to pulse conversion of the line signal (switched modes supplies could add noise here). The line frequency is not perfect, but also not that bad. So it might take a good PLL to get a stable clock from this. With the changes grid this might need improvements / modifications to the original PLL.

For first test a fixed frequency instead of the PLL is a good idea: residual 50 Hz coupling would than result in a very low frequency essentially single frequency background that is easy to distinguish from noise.

[e61_phil]

Today I cut the VCO from IC835 and fed 10.48576 MHz into pin 3 of IC835. Now, all jitter is gone. The force waveforms looks perfect and also the GLUG signals. Only one discrete 200ns timestep was seen on the GLUG signals. But that will correspond to the 5MHz clock.

And what happend to the noise? NOTHING!


I recap what is done until now:

- Power Supplies seems to be ok
- PLL voltage trimmed to 2.5V
- Input chain from bindung posts to the Integrator input seems to be ok -> it should be an ADC problem
- direct signal injection in the ADC shows noise and also Test0 mode -> more arguments for an ADC problem
- IC201 was replaced by a new one
- IC202 was replaced by a new one
- caps were added over IC202 to stabilize power supply
- zener voltage from D204 and D205 is stable
- C201 was replaced with a 100nF MKS -> no change at all
- TR201 and TR202 were swapped with others from others circuits
- TR203 and TR204 were swapped with others from other circuits
- 50Hz mains signal was replaced with 50Hz from signal gen to avoid drifting
- PLL circuit was disabled an 10.48576 MHz was fed in IC835 to remove jitter

There is still more than 10µVpp noise within 60s measurement with 7.5 digits

I think there is not much left to try? Perhaps, IC203, IC204 and IC205 Only these remain in the ADC circuit.

[Kleinstein]

Seem to be a rather tough challenge to get down the noise.
One thing might be doing a real noise measurement, to know better what noise is there. It looks like the ADC is continuously running and different resolutions / integration times are just a question of reading at different times or doing averaging in software, which would result in the same. So one would get the most information from taking data at a relatively high rate, but still not missing any conversions or too much resolution, and than do FFT on them.

C201 might still be an issue, as the original specified polypropylene type, not MKS. Through I would expect more like minor non-linearity from this.

If we are at caps, C212 might be critical too, if it shows leakage.

With the ICL7650 for IC201 there might still be a problem: this OP is known to show higher than specified noise in several cases. Though the noise from this OP should give something like 2 µV_pp in the 0-10 Hz range only. So for a 400 ms integration time this should be really low, even if several time the specified noise.

IC203/204 might also want local decoupling. Though I doubt they are the noise source, changing then could be relatively easy / cheap. There was not much jitter at the output of IC205, so I doubt this chip is at fault.

Another point might be the reference section. The ADC relies on the positive and negative 10 V refs to be connected. So noise in the ratio will show up as noise of the ADC, even if measuring 0. So IC306 is critical in this way though at nominal specs it only contributes something like 0.2 µV_pp for 0.1-10 Hz. The forcing waveform might give some dynamic load to the references and thus could give minute ringing that might also contribute.

Another point worth looking at might be the cross over of the two OPs in the integrator, I don't know how accurate the design is (likely done before spice simulation became popular). It might be worth simulating that part and see if it might react sensitive to tolerances in the caps or amplify noise from some bands.

p.s.: I did a short similation: the cross over and tolerances are not critical at all, so not problem here.

[e61_phil]

Seem to be a rather tough challenge to get down the noise.
One thing might be doing a real noise measurement, to know better what noise is there. It looks like the ADC is continuously running and different resolutions / integration times are just a question of reading at different times or doing averaging in software, which would result in the same. So one would get the most information from taking data at a relatively high rate, but still not missing any conversions or too much resolution, and than do FFT on them.

My plan was to measure the GLUG signals not only for a few seconds to possibly see any issues. I would try this first, because the output of my function gen is ground referenced. Therefore, my scope GND is now shorted to the -15V rail. This will restrict some measurements.

C201 might still be an issue, as the original specified polypropylene type, not MKS. Through I would expect more like minor non-linearity from this.

If we are at caps, C212 might be critical too, if it shows leakage.

What do you think about some linearity tests? I could use my Fluke 343A and my KVD (ESI RV722) to do some tests. First, I will set the KVD to 1.0000000 and tune the Fluke to 10.00000V on the Solartron. With some averaging it should be possible to test the linearity of the meter. Is it worth the effort? I think it will take some time to average the signal.

Another point might be the reference section. The ADC relies on the positive and negative 10 V refs to be connected. So noise in the ratio will show up as noise of the ADC, even if measuring 0. So IC306 is critical in this way though at nominal specs it only contributes something like 0.2 µV_pp for 0.1-10 Hz. The forcing waveform might give some dynamic load to the references and thus could give minute ringing that might also contribute.

I will try a ratio measurement with my 3456A and I can try to have a look with my Tek 7A22 (very long unused ).

Another point worth looking at might be the cross over of the two OPs in the integrator, I don't know how accurate the design is (likely done before spice simulation became popular). It might be worth simulating that part and see if it might react sensitive to tolerances in the caps or amplify noise from some bands.

p.s.: I did a short similation: the cross over and tolerances are not critical at all, so not problem here.

Great! Thanks

It is really great how much effort some people in this thread will invest to MY problems. And I have to apologize for my bad english.

[Kleinstein]

I just read the first part of the thread again. The noise does not look that bad from the descriptions, but it's also confusing. Sometimes it is not clear which mode is used. Also peak to peak values are little tricky, as they fluctuate quite a lot. The RMS values over something like 200 readings (the exact number does not matter much, but should be the same to compare) are more repeatable. Also drift during the run is of interest, as it adds to the RMS values.

So you are really after the least bit of noise, possibly even in spec for the 7071 model. So having good data on the noise might help to see if we look for a defect part or more like the difference between guaranteed specs and so called typical performance.
Especially in the high resolution modes it is expected to see some noise in the lower digits - that should be normal.

If the noise is a problem when reading a significant voltage, the reference could still be the problem. So a test with measuring the internal 10 V reference with the meter itself could help.

The ratio measurement with a 3456 meter will not really help - the noise might be below the noise of that meter.
Checking that the sum of the +10 and -10 V refs iis really close to 0 V could be done with the 3456, just with two consecutive measurements. One might also check the offset of IC306 directly. In case you want to upgrade with newer parts - IC306 might be a point where better parts (LTC2057 instead of OP07) are available though it's likely only a small improvement.

Linearity test to the performance of the meter are very difficult. So I would on the long term just change C201 to a PP type capacitor like specified. It's not such a special part to buy - I don't think you need low tolerance. I minimal test would be checking with a external reference signal and reversing the polarity. Still without a direct comparison to a good cap this will not help that much. Changing the capacitor type might influence the calibration at least it does so with high resolution dual slope converters. The linearity test is a different thing from the noise, so one problem at a time.

[e61_phil]

I just read the first part of the thread again. The noise does not look that bad from the descriptions, but it's also confusing. Sometimes it is not clear which mode is used. Also peak to peak values are little tricky, as they fluctuate quite a lot. The RMS values over something like 200 readings (the exact number does not matter much, but should be the same to compare) are more repeatable. Also drift during the run is of interest, as it adds to the RMS values.

So you are really after the least bit of noise, possibly even in spec for the 7071 model. So having good data on the noise might help to see if we look for a defect part or more like the difference between guaranteed specs and so called typical performance.
Especially in the high resolution modes it is expected to see some noise in the lower digits - that should be normal.

The noise is a factor of 10 higher in 6.5 digit mode. So 11µVpp will become 110µVpp for example. And if that is in spec, than I think it is a nearly useless 6.5 digit DMM. My 3456A is completely stable including the last digit even with only 10 NPLC connected to the Fluke 343A, Knick JS3010 or a LTZ1000. Therefore, I can't believe that this should be in spec.

I will do some RMS noise measurements. My LabVIEW file showed it already, but I didn't noted it...

If the noise is a problem when reading a significant voltage, the reference could still be the problem. So a test with measuring the internal 10 V reference with the meter itself could help.

I will do that. If the reading is stable, I would expect a noisy reference. But, I don't think so. I've measured the references already with the 3456A (silly me: I didn't compare +10V to -10V) and they were stable within the 6.5 digits of the 3456A.

The ratio measurement with a 3456 meter will not really help - the noise might be below the noise of that meter.

I think I should see noise down to nearly 1ppm with the 3456A on the 10V references. So if the noise is below 1ppm shouldn't the meter be stable in 6.5 digit mode? Another question of mine is: Why should a noisy reference influence the reading of 20µV by 50%? Should reference noise not appear in the same relative dimension on the output?

[Kleinstein]

Noise of the reference itself should not influence the reading of a small voltage very much. A difference thing would be noise that shifts the +10 V and -10 V reference signal together. This will essentially appear like in the signal, as the 0 V is mainly a compensation of the +10 V and -10 V.

As the +10 V and -10 V are used one after another, there is also a way that higher frequency (e.g. 160 Hz range) noise of the reference will add to the ADC noise, when measuring signals near zero. As the plan shows essentially no filtering for the zener noise, one might think about adding some (e.g. a capacitor from GND to IC305 pin 2, or across the zener diode).

As far as I understood the specs are < 20 µV_pp for the 10 V range. For the noise sources I looked at so far I would expect something like:
1 µV_pp from IC201 (ICL7650), possibly more as specs of ICL76650 are rather optimistic
3.5 0.35 µV_pp from IC202 (LM301) - current noise, some variations possible as not all LM301 are the same
0.35 µV_pp from IC305 (OP07)  - this might get critical for 7.5 Digit mode due to 1/f part.
0.4 0.3 µV_pp from the resistors (R221,R201,R202)
e.g. 0.3 µV_pp from 160 Hz band noise of Zener diode (assuming 50 nV/Sqrt(Hz) for the zener), hard to estimate.

Looking at the comparators might also be worth while. Due to the rather large 100 nF integration cap, the slope is rather slow and thus the comparator delay at low overdrive could be tricky.

[e61_phil]

As far as I understood the specs are < 20 µV_pp for the 10 V range.

That sounds really bad . But it is "only" 2ppm pp at 10V



I did some further measurements:

+10V Ref: 9,90954 V
-10V Ref: 9,90958 V
That is much better than the printed 0.005% and the Vishay divider. During measurement I swapped the leads in a way, that the 3456A sees only positive voltages, to get a more reliable result. The reading was done with 100NPLC and was stable.


I made 200 Measurements of the positive reference voltage:

6.5 digit mode: 5.05ppm pp and 1.23ppm RMS
7.5 digit mode: 2.42ppm pp and 0.29 ppm RMS

It seems to me like more than the spec allows. The measurement was done with an open case to access the reference voltage. But measurements in the pasts doesn't show any difference with an closed case.


Next, I will replace IC203 and IC204 with new LM311.

[Kleinstein]

The reference readings look good. So no big trouble there. Though there is still a chance that the reference might have quite a lot of noise. Noise specs for the reference are hard to estimate, but zener diodes are known to be somewhat noisy.

The noise reading really look not that good:  for the 6.5 digit mode the RMS value is about 4 times the specs of the 7081. As the 7081 are better tested, a slightly higher noise for a 7071 model is possible.
The noise in the 7.5 Digit mode is about 1/4 from the 6.5 digit mode - this is indicating that the excess noise does not have a strong 1/f character. The only 8 times longer integration time would even expect only a 3 times reduction in noise for a white noise source, though a little may come from less quatisation-noise due to the extra digit.

I checked my calculations for the noise - was a little late yesterday: I found that the noise of R221 should not contribute as much as expected - forgot the AC coupling for it, so a little less there. The cap might also reduce the noise from the 160 Hz range of the reference - have to rethink that.
Also estimate for the current noise of IC202 was wrong by a factor of 10, so much lower contribution there - sorry. Sill some uncertainty there, as the 1/f noise can vary quite a lot between individual chips. Newer LM301 might be better without notice.
So I change the numbers above.

The main result is the same: there are some noise sources, but the seems to be other import ones still not in the list.
So looking at the comparators is a good idea. If the slow slope is a problem for the comarators - there might be the option to use an extra amplification stage between the integrator and comparators - other meters like 3458 or keithly 2000 use this trick.

[e61_phil]

Today I replaced IC203 and IC204 with new LM311. Still nothing changed. The noise in 6.5 digit mode is still 60µVpp and 23µV RMS with a closed case. (Back to PLL)

Furthermore, I desoldered C212 for a quick leakage test and put it in series on a 40V supply (Knick Calibrator) with my 3456A in 100V Range (to get 10Meg input resistance) the 3456A went to 0 after some time. So less than 100µV over 10Meg -> less than 10pA.

All of your improvement ideas are really great, but in the first place I want to get the meter in spec with the original circuit.

[Mickle T.]

I was thoroughly reread a notebook with my handwritten notes about 7081's research and modding. One day the 7081#1 suddenly increased noise amplitude with factor of 4-5. Intercomparison with a normal 7081#2 gives nothing: DC modes, waveforms are almost identicals. Also the TR201, 202 swapping with 7081#2, changing IC201 to LTC1052, IC202 to LME49710 or OPA604 gives nothing too. The only thing that suddenly stops the excessive noise is touching a IC307 (DG301) pins with a hot soldering iron 

[e61_phil]

I was thoroughly reread a notebook with my handwritten notes about 7081's research and modding. One day the 7081#1 suddenly increased noise amplitude with factor of 4-5. Intercomparison with a normal 7081#2 gives nothing: DC modes, waveforms are almost identicals. Also the TR201, 202 swapping with 7081#2, changing IC201 to LTC1052, IC202 to LME49710 or OPA604 gives nothing too. The only thing that suddenly stops the excessive noise is touching a IC307 (DG301) pins with a hot soldering iron 

Very interesting and simultaneously annoying that even with a second meter side by side the source of the noise wasn't traceable by measurements.

I touched severels pins of IC307 but nothing changed. Afterwards, I resolder the IC and still no change. Perhaps it might be a good idea to order a new DG301.

[e61_phil]

A DG301 in a ceramic package is not that easy to get and expensive. What do you tink? Is it worth to give it a try with a plastic one from vishay or maxim (Farnell)?

Unfortunately, I will cut the pins of the DG301 to get it out without the risk of damaging the PCB. Therefore, I will have a plastic DG301 after this test.

[Mickle T.]

There is no need to break out the old chip: disconnect R310, R311 and connect new chip to its.

[Mickle T.]

Some info about ADC:

[Kleinstein]

The plastic package for the DG301 should be no problem, as properties like leakage or on_resistance are not critical for this part - it's only AC Coupled. The important property is having low jitter from input to output and short time stability of on_resistance only.

[e61_phil]

A new DG301 doesn't changed anything..

[Mickle T.]

Well, it's time to isolate an analog part of ADC and change it to some external waveform generator.

[e61_phil]

Well, it's time to isolate an analog part of ADC and change it to some external waveform generator.

Could you describe a little bit more what you expect to do?

[wiss]

Some info about ADC:

Thanks!

[Mickle T.]

Could you describe a little bit more what you expect to do?

The problem may lie in the digital section only.

[e61_phil]

Could you describe a little bit more what you expect to do?

The problem may lie in the digital section only.

And in which section do you think? And is it easy possible to simulate the ADC with an arb function gen?

The section under this shielding PCB gets quite wam.

Next I will have a closer look at IC205 and the signals which goes to the digital section.

[Mickle T.]

And in which section do you think? And is it easy possible to simulate the ADC with an arb function gen?

[e61_phil]

Are these two different tests? And what kind of result I should see? Sorry for my stupid questions

[Mickle T.]

The first picture only. It is possible to test a counter/interrupt/e.t.c. logic section of ADC with isolated analog one.

[e61_phil]

The first picture only. It is possible to test a counter/interrupt/e.t.c. logic section of ADC with isolated analog one.

I should use a function generator to create a puls with a period < 3 ms and trigger this pulse from "FW PL501/11"?
Do I understand it right?

Should it be 50% dutycycle? And what effect has a change in periodtime or/and dutycylce?
And where can I get this "FW PL501/11" signal to trigger the pulse?

[Mickle T.]

I should use a function generator to create a puls with a period < 3 ms and trigger this pulse from "FW PL501/11"?

You are absolutely right. The value of dutycycle is not important as you explore the noise/short-term stability.

[e61_phil]

And some more measurements..

I used the signal from pin 9 of U833 to keep the DG301 out of the measurement. With this signal I triggered my function gen. The function gen creates a 1.5ms puls with a 1.5ms delay after the trigger. This setup is shown in SP201_SP202_vs_force.PNG . The scope is also triggered to the force signal. Yellow is the signal on SP201 and blue on SP202.

I think that is the setup Mickle described.

In this setup the measured voltage is drifting. My first guess was the PLL circuit. Therefore, I measured the force signal frequency simultaneously (drift_vs_frequency.PNG). This means I have to get rid of the PLL again for this measurements.

[Mickle T.]

But how about the noise in the measured voltage?

[e61_phil]

But how about the noise in the measured voltage?

I couldn't measure it. The drift was much higher between two measurements than the noise.

[e61_phil]

Today I used my HP 8165A to feed 10.48MHz (no more resolution available on the HP 8165A) into pin 3 of IC835. Afterwards the drift is gone but it is still noisy.

The noise is even a bit higher as with the real ADC? So I don't know how to interpret this. The noise within 200 6.5 digit measurements is now about 51µV RMS and 280µVpp.


Edit:
To get -1V instead of 0V on the Solartron I have to reduce the pulse width by about 200ms. Therefore, a change of 10µV needs a change of 2µs in pulse width. I've measured the pulses from the siglent and the jitter is in the region auf 10ns. So far too small to induce this noise. The 10.48MHz out of the HP gen aren't that stable, but I think that isn't a big problem, cause the HP generates the "master clock" with the force waveform which is then synced with the siglent.


Edit 2:
I saw a ~100ns jitter on the GLUGS signal and the ~5MHz signal at pin 9 of IC205 is also jittering/drifting 1.5ms after the force signal edge. So I decided to get rid of the HP 8165A and use my 10MHz DOCXO. I think 10.48 or 10.0MHz shouldn't matter anything because in the digital part we don't have to reduce any mains frequency related noise.

After some breadboarding to get a TTL signal out of the DOCXO the noise is gone (not tested with the real ADC yet!). Also the 200ns jitter in the GLUGS signal is gone.


Edit 3:
I kept the DOCXO for the clock an resoldered SP201 and SP202. The noise is still the same

One can see know again these 200ns jitter on the GLUGS signals. Perhaps it may cause more issues than expected?

[acbern]

Wow!  I was just thinking that given the level of difficulty in just *repairing* an instrument capable of sub-ppm resolution, I can only conclude that it must have been [and still would be] extremely difficult to *design* such an instrument.  This compels me to have a whole new and higher level of respect for those engineers that designed these high resolution instruments.  It's really quite amazing!

True blue. So there is a good reason why there is no new 3458A on the horizon. And that although the 3458A will no longer be sold in the EU starting 2017 thanks to ROHS regulations (thank you EU for solving a non existing problem for us; not the first one)

[Kleinstein]

Hunting down such a small amount of noise is really hard.

I don't think the error is in the digital section, e.g. the counters. A defect there should usually give a signal different from normal noise. Even if some timing is just on the edge this would give more like 1/f noise and dependence on temperature.
There could still be a problem with the PLL part, e.g. a frequency that is not stable and this way gives some noise. I would consider using a 10 MHz crystal clock for a test, even if it is significant off from the 10,48 MHz. This would reduce the 50 Hz / 100 Hz suppression, but residual 50/100 Hz would be different from noise - though it might need a FFT of the data to see it.

Even without any modification a FFT on the noise data might be a good idea, to see if is really white noise or maybe coupling of some frequencies (e.g. the switched mode converter for the 5 V supply).

One point worth checking might be the opto-couplers. They tend to age and than might not give full signal.

[wiss]

Have you established that the clock is stably locked to line-frequency?
Set a scope to line-trig and lock at the forcing waveform or something like that?

[e61_phil]

Hunting down such a small amount of noise is really hard.

I don't think the error is in the digital section, e.g. the counters. A defect there should usually give a signal different from normal noise. Even if some timing is just on the edge this would give more like 1/f noise and dependence on temperature.
There could still be a problem with the PLL part, e.g. a frequency that is not stable and this way gives some noise. I would consider using a 10 MHz crystal clock for a test, even if it is significant off from the 10,48 MHz. This would reduce the 50 Hz / 100 Hz suppression, but residual 50/100 Hz would be different from noise - though it might need a FFT of the data to see it.

I tried that already briefly with no success. I will repeat this experiment more careful.

Even without any modification a FFT on the noise data might be a good idea, to see if is really white noise or maybe coupling of some frequencies (e.g. the switched mode converter for the 5 V supply).

On which data should I run the FFT? On the 6.5 digit data from the GPIB interface?  I will try that, too. I will record some data with the PLL circuit and some data with the 10MHz crystal.

One point worth checking might be the opto-couplers. They tend to age and than might not give full signal.

The communication opto-couplers towards the earthed side? I think this error should stay even without the real ADC, but the noise is gone with a good clock and without the real ADC.

Have you established that the clock is stably locked to line-frequency?
Set a scope to line-trig and lock at the forcing waveform or something like that?

Nice experiment . I will try that.

[e61_phil]

Have you established that the clock is stably locked to line-frequency?
Set a scope to line-trig and lock at the forcing waveform or something like that?

I did that experiment. The result is shown in the attachment. The blue trace is the 10Hz signal at TP607 and the yellow trace is the 160Hz ADC signal.

It shifts around, but the mains frequency isn't constant here. So, if the mains frequency will shift the PLL filter can't react immediately. For me it seems like a normal PLL operation?

[wiss]

Have you established that the clock is stably locked to line-frequency?
Set a scope to line-trig and lock at the forcing waveform or something like that?

I did that experiment. The result is shown in the attachment. The blue trace is the 10Hz signal at TP607

Isn't the forcing 10 kHz? I'm pretty sure it is that on the 7075 anyway.

and the yellow trace is the 160Hz ADC signal.

are you on 50 or 60 Hz line?
160 Hz can not be synchronous with either.

It shifts around, but the mains frequency isn't constant here. So, if the mains frequency will shift the PLL filter can't react immediately. For me it seems like a normal PLL operation?

Yea, at least the 10 Hz stay within a fixed phase-shift.

On my 7075 I can see a static 10 uV shift when I fail to ground properly, a non-synchronous DVM will drift significantly (10s of uV) under the same conditions.

[e61_phil]

Have you established that the clock is stably locked to line-frequency?
Set a scope to line-trig and lock at the forcing waveform or something like that?

I did that experiment. The result is shown in the attachment. The blue trace is the 10Hz signal at TP607

Isn't the forcing 10 kHz? I'm pretty sure it is that on the 7075 anyway.

and the yellow trace is the 160Hz ADC signal.

are you on 50 or 60 Hz line?
160 Hz can not be synchronous with either.

It shifts around, but the mains frequency isn't constant here. So, if the mains frequency will shift the PLL filter can't react immediately. For me it seems like a normal PLL operation?

Yea, at least the 10 Hz stay within a fixed phase-shift.

On my 7075 I can see a static 10 uV shift when I fail to ground properly, a non-synchronous DVM will drift significantly (10s of uV) under the same conditions.

I'm on 50Hz mains. The forcing waveform is 160Hz.

The falling edge of the 10Hz is locked to 50Hz mains. The rising edge is shifting.

[wiss]

Could you explain to me how the forcing is clocked?
where does CLK come from?
IC814 divide by 100 and IC815 divide by ?, right?
IC833 make IC815 divide by some other number > 10, right?

[wiss]

It's not that the PLL-feedback-loop is oscillating?

[Kleinstein]

The 10 Hz Signal looks suspicious: the falling slope seems to be locked to the line frequency, but the rising slopes look like having lots of jitter. It looks so bad it might be visible just from the 10 Hz or 160 Hz signal alone.

For me this does not look like normal operation for the PLL. More like lots of line synchronous signal coupled to the PLL.  So I would check/replace C814, C812 and check or test some shielding of the PLL section.

It might be also interesting to see the signal at TP807.

[wiss]

Now I realize where I've seen you before
The 192 is still doing it's work, now mostly 4 terminal resistance measurements when needed.

I've seen ceramic caps decrease in value (~10%), maybe even replace all frequency setting caps in the PLL-oscillator subcrct?

[e61_phil]

It might be also interesting to see the signal at TP807.

Sorry, the blue trace shows TP807 not TP607.

Now I realize where I've seen you before
The 192 is still doing it's work, now mostly 4 terminal resistance measurements when needed.

That was another meter with jumping last digits . If I remember correct the problem was a resistor array?

The 10 Hz Signal looks suspicious: the falling slope seems to be locked to the line frequency, but the rising slopes look like having lots of jitter. It looks so bad it might be visible just from the 10 Hz or 160 Hz signal alone.

For me this does not look like normal operation for the PLL. More like lots of line synchronous signal coupled to the PLL.  So I would check/replace C814, C812 and check or test some shielding of the PLL section.

It might be also interesting to see the signal at TP807.

To get rid of the whole PLL circuit I cut (again) pin 5 of IC835 and fed in 5.24288 MHz with a jitter of a few ns. The noise stays.. Did I miss a thing, which will get its frequency not out of the CLK net?

Why did they use these frequencys? The 5.24288 MHz and the 160Hz are not multiples of 50Hz. So, how does the mains rejection work?

[wiss]

Now I realize where I've seen you before
The 192 is still doing it's work, now mostly 4 terminal resistance measurements when needed.

That was another meter with jumping last digits . If I remember correct the problem was a resistor array?

The divider for the reference was bad, and then one of the switching JFETs was leaking, for the AC-unit so I just amputated that.
Had it been subjected to neutron radiation? 

The 10 Hz Signal looks suspicious: the falling slope seems to be locked to the line frequency, but the rising slopes look like having lots of jitter. It looks so bad it might be visible just from the 10 Hz or 160 Hz signal alone.

For me this does not look like normal operation for the PLL. More like lots of line synchronous signal coupled to the PLL.  So I would check/replace C814, C812 and check or test some shielding of the PLL section.

It might be also interesting to see the signal at TP807.

To get rid of the whole PLL circuit I cut (again) pin 5 of IC835 and fed in 5.24288 MHz with a jitter of a few ns. The noise stays.. Did I miss a thing, which will get its frequency not out of the CLK net?

Why did they use these frequencys? The 5.24288 MHz and the 160Hz are not multiples of 50Hz. So, how does the mains rejection work?

the 7081 do not use 1 s integration so no need to have multiples of 50, the forcing is 160 or 640 Hz, I think i figured out.
the forcing and the main clock and the line frequency need to add up over one integration cycle, there will be 4 forcing cycles of the 6 ms integration.
If the phase of the 50 Hz drifts relative the integration you will get noise unless you have very good shielding. The 50 Hz is only 4 digit stable so max 80 dB attenuation (?) without phase-lock. (Yes I did almost call up the local power company tom complain about the 49.99 to 50.01 Hz variation )

[Kleinstein]

The sampling period (400 ms if I understand it right)  is a multiple of the 20 ms line period (at 50 Hz) and the forcing signal period. So there is an integer number of periods of both signal. It might be intentional that the 160 Hz causes transitions at several positions of the 50 Hz line signal.

I don't know why they choose this strange frequency - it should have worked with other frequencies (e.e. 12 MHz) as well. The main part for the PLL is to get the forcing signal and the sampling period synchronized to the line frequency.

With the 10 Hz signal beeing from TP807 - this signal does not look that bad. The output of the phase comparator shows how much jitter is there between the line signal and the PLL output. So something like 4 µs pulses don't look really bad - though it is somewhat strange to see something that looks like missing pulses and than pulses from 2-4 µs, but no shorter ones and no negative ones. Could be due to the rather slow IC824 = CD4046 ( today I would use the faster 74HC4046).

With the fixed clock frequency one should take a few more data via GPIB and check via FFT if the "noise" is white or contains a dominant low frequency.

[e61_phil]

Yes, 6.5 digit takes 400ms.

I've attached the FFT. I've collected data from 1600s of 6.5 digit measurements (~4000 data points)

I think there is no significant peak

[alanambrose]

Interesting - btw how did you do the fft? - I want to do something similar.

TIA, Alan

[e61_phil]

Interesting - btw how did you do the fft? - I want to do something similar.

TIA, Alan

I simply used the power density FFT function included in NI LabVIEW.

[Kleinstein]

The FFT looks somewhat unusual: one normally expects to have more noise at lower frequencies. like a white part and and 1/f part. Having much of the noise at the higher frequencies somewhat points to a problem in using a well defined integration time or reaching a stationary signal from the forcing signal. The errors of the single conversions somehow compensate.

So I won't expect a problem with the FET switching (Tr201-Tr204) or the digital counters at the glug signals (of the as errors from that part would add up. Also the integrator seems to work - at least a low frequencies - so IC201 and IC202 should work OK. The comparators or there supply could be still a source of trouble.

It does not look like trouble with insufficient 50 Hz suppression and to much hum at the input, as this should give some signal somewhere below 0.1 Hz. Though coupling from higher line harmonics might shift the signal to higher frequencies. So the fixed clock should not be the problem.

I might be worth looking at the integrator output (using the forcing signal as trigger) - the noise suggests that there is more jitter/fluctuations than it should be.

It could still something in the forcing waveform - but not much left there. Have you checked there is not jitter in the operation of IC307 (e.g. from a not so perfect digital signal) ?

I would keep in mind C201 and get a MKP (or better) capacitor for this. You will likely need it to get good linearity anyway.

[e61_phil]

The comparators or there supply could be still a source of trouble.

I already replaced the LM311 against new ones. I measured again the supply voltages and it looks ok. Nevertheless, I installed some 1µF MKP directly on the LM311's, but that doesn't change anything

I might be worth looking at the integrator output (using the forcing signal as trigger) - the noise suggests that there is more jitter/fluctuations than it should be.

I had a quick look and it seems to be stable. A jitter is hard to see because of the flat integrator signal.

It could still something in the forcing waveform - but not much left there. Have you checked there is not jitter in the operation of IC307 (e.g. from a not so perfect digital signal) ?

I replaced IC307 with a new one, but I will check the operation again.

I would keep in mind C201 and get a MKP (or better) capacitor for this. You will likely need it to get good linearity anyway.

I put the original 100nF back into the unit




Hmm, I'm beginning to think I'm doing something really stupid..

[wiss]

Could you measure the pll control voltage and do a fft of that? And compare to the measurement fft.

[e61_phil]

Could you measure the pll control voltage and do a fft of that? And compare to the measurement fft.

During the FFT measurements I didn't use the PLL. I fed in 5.2488MHz from my function generator.


The PLL voltage is shown in https://www.eevblog.com/forum/metrology/solartron-7071-7081-last-digit-is-jumping-all-over-the-place/msg871006/#msg871006  but without a FFT

[wiss]

I do not like the ragged part after 200 s but I can not say that it is wrong.
The PLL in my 7075 is similar, I could take a look after the weekend, unless someone can post that voltage from a working 7081.

[Kleinstein]

With the measurement done at fix clock, the PLL is essentially out as a noise source. Though a not so stable clock from the generator might be a problem.

I know that the Comparators and IC307 for the forcing signal is already changed, but these two circuit areas are still the two main suspects to me.

For the forcing waveform this could still the signal level that goes to IC307 - going from TTL to CMOS is sometime just on the edge of working for the high level. But if this is a problem is should be visable as jitter (something like 100-1000ns) at the forcing waveform - thus much more than expected from the chip (e.g. 1 ns level).

For the comparators there are a few possible causes for trouble: The noise of the LM311 is usually not specified and not all manufacturer might give chips that are really good here. The second part is the supply. The hysteresis part adds some portion of the supply back - so this part could be very sensitive to noise on the supplies. The negative supply is somewhat coupled to ground via C223. Thus adding caps directly to the supply might couple noise to this ground and though good for the chip, might cause trouble too. The other supply that enters is the negative 10 V - that might contain some HF noise from the TTL chips also using this. One test here could be using a larger hysteresis (e.g. 10 K parallel to R217/R218) - if the supply noise coupled though R217/R218 is a problem, the noise should get larger by about a factor of 3 from this.

[wiss]

My 7075 has ~10 mV sub-second variations on the control-voltage for the PLL and the 3.2 MHz varies about 1 kHz on the same times-cale.

Red curve is the control voltage green the frequency.

First picture is control voltage and pll-frequency.

Second picture is control voltage and 50 Hz (sync) frequency.

First time I hooked up my counter to the GPIB-system

[e61_phil]

With the measurement done at fix clock, the PLL is essentially out as a noise source. Though a not so stable clock from the generator might be a problem.

I know that the Comparators and IC307 for the forcing signal is already changed, but these two circuit areas are still the two main suspects to me.

For the forcing waveform this could still the signal level that goes to IC307 - going from TTL to CMOS is sometime just on the edge of working for the high level. But if this is a problem is should be visable as jitter (something like 100-1000ns) at the forcing waveform - thus much more than expected from the chip (e.g. 1 ns level).

For the comparators there are a few possible causes for trouble: The noise of the LM311 is usually not specified and not all manufacturer might give chips that are really good here. The second part is the supply. The hysteresis part adds some portion of the supply back - so this part could be very sensitive to noise on the supplies. The negative supply is somewhat coupled to ground via C223. Thus adding caps directly to the supply might couple noise to this ground and though good for the chip, might cause trouble too. The other supply that enters is the negative 10 V - that might contain some HF noise from the TTL chips also using this. One test here could be using a larger hysteresis (e.g. 10 K parallel to R217/R218) - if the supply noise coupled though R217/R218 is a problem, the noise should get larger by about a factor of 3 from this.

Today I desoldered the 1µF caps from the LM311s and put 10k in parallel with R217 and R218. The measured noise was 16µV RMS and without these resistors it was the same.

I also measured the forcing waveform drive signal against pin 4 of IC307. There was no jitter.

[Kleinstein]

Today I desoldered the 1µF caps from the LM311s and put 10k in parallel with R217 and R218. The measured noise was 16µV RMS and without these resistors it was the same.

I also measured the forcing waveform drive signal against pin 4 of IC307. There was no jitter.

So this would exclude two more possible error sources.

There still is the question whether the noise is due to a defect (parts well out of specs) or just due to the normal design weakness and possibly parts at the lower end of specs. Remember that the 7071 is the less tightly tested / lower spec version.

For me the main suspects would be the comparators switching at the wrong time sometimes.  I don't expect the LM311 to be so noisy - my rough estimate would give something like a 100 ns uncertainty, which would be something like a +-1 count. So some contribution (e.g. 0.2 ppm for the 6 digit more), but not much.  But one never knows - it's a low cost part made by many sources, and not all have exactly the same specs. Though chances are low, one could test different LM311 chips.

Another point might be noise on the ground line 0V(s)1 , from C223 to ground. If there is more noise than expected on the supply (+15V) this could get coupled here. To me the supply decoupling around IC202,IC203,IC204 does not look very good solved. usually not having local decoupling on a LM311 is a bad sign, but if there this might couple noise to a sensitive ground line. For me the logical solution would have been having a kind of resistor/inductance in the positive supply and than have local decoupling.

 

[e61_phil]

I still can't believe that this meter will be in spec. It will be a complete useless 6.5 digit meter. Unfortunately, I only found noise limits for the 7081.

Perhaps I should think about a test circuit for the LM311.

What do you think about removing IC202 and fed a voltage from a calibrator into TP201 (Integrator) and look at the comparators output? I can record the hysteresis (hopefully).

Another test could be a puls from a function generator into TP201 to measure the jitter of the LM311.

[wiss]

I still can't believe that this meter will be in spec. It will be a complete useless 6.5 digit meter. Unfortunately, I only found noise limits for the 7081.

the older 7075 is spec'd to +- 1 count at 1 s integration for 10 readings and 10 V in, I can not believe that the 7071 is worse than that...

[Kleinstein]

To check for jitter from the LM311, one could trigger the scope on the output of the LM311 and look at the input signal. This could be tricky, as the voltages are really small, so a normal scope will not see much. The trouble is there is not that much noise needed to upset the comparators. The integrator output is rather lowly changing (e.g. 250 V/s) so it only takes some 250 µV to delay the comparator by 1 µs. This rather small signal will be problem with a separate test jig too.

One way to exclude / reduce noise from the comparators would be to give them an amplified signal. E.g. have a small amplifier (e.g. 10 fold amplification for small signals, down to 1 for a large signal) between IC202 and the comparators. This addition might be easier than an extra test jig for the comparators. 

It might also be interesting to have the scope triggered from the forcing signal and look at the outputs of the comparators. Ideally there should be not more than about 100-200 ns of variations due to the clocked feedback.

From looking at the counter in the digital section, I can no see (at least if the circuit is as in the plan, they could have done different !) a way a mistake there would add noise to individual conversions, but not effecting the long time average.

It might be a good idea to check the old data again, by plotting a histogram. The distribution of values might give more clues about the origin of the errors - could be still a few measurements that are off by a lot or more normal noise.

It might also help to compare the noise in the 5 digit mode. Here the date are from shorter times and thus might show the trouble even stronger. The higher forcing frequency might give some more information. Here it should also be more clear if the noise is really to high.

With the 5 digit mode one could also do a test on the effect of the forcing waveform. With a smaller resistance (e.g. 22 K in parallel) for R221 one would get a stronger forcing signal. This should result in more noise if the forcing part is the problem. It's difficult to do the test in 6 digit mode, as the integrator might saturate.

[e61_phil]

Unfortunately, I had no time the last days for further measurements. However, I read a post in the volt-nuts mailinglist about the difference between the 7071 and 7081. The message was: only the frontpanel and the reference diode selection will differ. The best reference diodes went into the 7081 and the others went into 7071 models.

Furthermore, I asked one to measure the Peak-Peak noise in the 10V range in 6.5 digit mode on his 7071 (he hasn't any GPIB or RS232 cables). And he measured 60µVpp in about 40min. This result isn't much better than mine.

Perhaps Kleinstein is right with his idea that this noise could be in spec for a 7071?

Could anyone with a 7071 reproduce this test?

And could it be the case, that this increased noise is induced by a worser reference zener? Or is it more likely, that other parts are also worse in a 7071 meter (by selection)?

[Kleinstein]

More noise from the reference diode is unlikely to have much influence on the readings with shorted input / reading zero. Due to the forcing signal, the noise in the 160 Hz Band of the reference can still have some influence. As this is higher than the typical 1/f noise region, so only a really noisy reference would give so much noise that it would really be visible. Something like a 100 nV/Sqrt(Hz) noise (e.g. about what a LM399 or LM329 have) from the reference would cause something like 0.8 - 1 µV_pp for the 400 ms integration time of the 6 digit mode.  Noise of zener diode varies a lot, but it would need a really noisy one to get in the 50 µV region. Also the noise would have a more or less white spectrum. Thus does not match the observed FFT.

The noise spectrum looks like the noise is somewhere in the timing of the comparators. So the observed noise is expected to be considerably worse in the 5 digit more and not that bad in the 7 / 8 digit mode. Doing a short calculation gives a not so small contribution for the noise from the LM301 and LM311. The LM301 is specified at about 15 nV/Sqrt(Hz). The LM311 has comparable bias and thus is expected to have a similar, maybe slightly lower noise. So together this is something like 20-25 nV/Sqrt(Hz). The bandwidth should be somewhere in the 10-15 MHz region, again a little hard to estimate. This would give a 60-80 µV_rms noise for the trigger level. At a slope of about 200 V/s this would correspond to something like a 0.2-0.4 µs jitter for the comparator. For a 0.4 s integration time and jitter at both ends this could give a noise in the 1 ppm = 10 µV_RMS range. So peak-peak values of 50-60 µV sounds reasonable and to a large part explainable to the noise of these two chips.

I don't expect so much scattering in the quality of the LM301 and LM311, even though the LM311 usually has no noise specs. The good thing is that it might be easy to test an upgrade to the LM301 by just drop in of a better OP (leave pin 1 open). The LM301 is not that bad, but there are modern JFET based OPs with lower noise. For a test even OP27/LT1007 would be an option - current noise might be a problem for the 8 digit mode.  If you order parts, one might also consider testing a different manufacturer for the LM311 - they are not expensive.  One could also do a test using a slightly smaller (or larger) integration cap (e.g. 68/200 nF instead of 100 nF) - this should reduce (or increase)  the noise from the LM301 and LM311s, though may increase settling time and nonlinearity.

[barnacle2k]

I fully characterized the noise on my Solartron for the DMM noise thread, the results should be somewhere in there. (all ranges all, all digits)

Noise for 10V range and 6.5 digits was 23.5uVpp, measuring window ~40minutes (6000 samples) .

[e61_phil]

I fully characterized the noise on my Solartron for the DMM noise thread, the results should be somewhere in there. (all ranges all, all digits)

Noise for 10V range and 6.5 digits was 23.5uVpp, measuring window ~40minutes (6000 samples) .

Thanks I will have a lokk into the DMM noise thread.

But, how can you measure 23.5µVpp with a resolution of only 10µV?

[Mickle T.]

This is the average value over 6000 samples. IMHO for a such long interval peak-to-peak measurement is almost useless due to thermal drift e.t.c.

[barnacle2k]

In 10V 6.5digit mode there is no visible drift in that timeframe.
There are only 4 discrete values in the data.

I used floating point output format over rs232. 
All my data can be found as CSV's on TiN's ftp if you want to analyze it yourself.

Code: [Select]

ftp://datashort:datashort@ftp.xdevs.com/barnacle2k

[e61_phil]

In 10V 6.5digit mode there is no visible drift in that timeframe.
There are only 4 discrete values in the data.

I used floating point output format over rs232. 
All my data can be found as CSV's on TiN's ftp if you want to analyze it yourself.

Code: [Select]

ftp://datashort:datashort@ftp.xdevs.com/barnacle2k

Thanks! Very interesting data.

Has anyone with a 7071 (not 7081) a similiar data set? (10V range would be sufficient)

[e61_phil]

Today, I want to do some drift measurements and I though "switch the filtering on and ignore the noise at first". The filtered measurement looks fine until the meter readjust the zero

[wiss]

How does the 7081 auto-null? I can not find any breaks in the input circuit...

Edit:
By opening RL5 and closing RL4?
Does RL4 close properly?

[e61_phil]

How does the 7081 auto-null? I can not find any breaks in the input circuit...

Edit:
By opening RL5 and closing RL4?
Does RL4 close properly?

I would think it measures zero by closing TR516 and TR517 like in Test0 Mode. And if it takes only one measurement for zero, the unfiltered noise will be added to the signal. That would explain the steps in the signal.


I've also attached a FFT measured in 5.5 digit mode (~32000 samples). I've averaged the sampling time, because due to the PLL the sampling time isn't excatly 100ms all the time (+/- 5ms).

[wiss]

I would think it measures zero by closing TR516 and TR517 like in Test0 Mode. And if it takes only one measurement for zero, the unfiltered noise will be added to the signal. That would explain the steps in the signal.

Thanks!

I've also attached a FFT measured in 5.5 digit mode (~32000 samples). I've averaged the sampling time, because due to the PLL the sampling time isn't excatly 100ms all the time (+/- 5ms).

Your line frequency varies by +-5%?

[Kleinstein]

The observed noise at  e61_phil's DMM agian shows the strange increase to higher frequencies also in 5 digit mode.  As expected the amplitude is comparable when comparing the same frequency. So the higher forcing frequency at least does not make things much worse. The data values are correlated and the filtering is thus more effective than normal (e.g. with white noise) to suppress the noise. So no surprise to find quite good data after filtering.

The data show something like 3-5 times the noise as the data from barnacle2k - assuming these data are measured without filtering. At least for the higher resolution modes ( 7 and 8 digits)  there could be minor differences in the software that might lead to slightly lower noise due to a subtile form of filtering.
It might still be interesting to see a FFT of these data, especially the 6 digit mode, to see if they show the same correlation. It might be a little difficult to see, as the quantization noise is of similar size.

Form the PDF linked above, one possible problem might be due to to little forcing signal - this might make the integrator plus PWM feedback part not getting fully stable. One could test this with something like a 10% more forcing (e.g. 390 K in parallel to R221). Other Solartrons even have a pot to adjust the forcing strength to find an good value - so maybe this one is just ad the edge.


5% variations would be way to much for the PLL. Is this real, or just a problem in measuring the time data are coming in ?

[wiss]

I saw data for the variations https://en.m.wikipedia.org/wiki/Power_quality, this agrees with what I saw myself, maybe +- 0.2 Hz variation,  no way as high as +-2.5 Hz. I measured with a 10 ms gate-time.

Edit:
Here is data, 10 ms gate-time on the counter, x-axis in seconds.

[e61_phil]

I've measured the 160Hz signal in https://www.eevblog.com/forum/metrology/solartron-7071-7081-last-digit-is-jumping-all-over-the-place/msg885093/#msg885093
The variation was about 1000ppm.

The sampling time measurement is done by labview. Normaly it is stable to about 1ms. I also tried the same VI with my HP 3456A and I can go down to 15ms and it is stable to 1ms. Perhaps, this is no issue and only a different way of data communication? In LabVIEW I measure the time between two instrument readings. Unfortunately, there is no VMC (volt meter complete) output like on HP DMMs. I will test it tomorrow with a clock out my function gen.

The meter gets quite warm inside if you run it closed. Is that normal? It think the electronic under this PCB shield (digital stuff) reaches about 40°C.

I will test the stronger forcing signal tomorrow.

Another thing was the foldback amplifier. Doesn't it decrease the linearity? And what about more modern comparators? I think I will give up with finding the error without changing anything on the original circuit. I think it is time for modern improvements. What is your opinion?

I also measured the 10V reference. There is plenty of distortion from anything correlated with the forcing frequency (but shifted in time). Are you sure that will cancel out completely? Is it perhaps worth to desolder TR301 and feed in 10V from my Fluke 343A into TP302?

[Kleinstein]

The extra amplifier between integrator and the comparators should not have much effect on linearity. It is more like a way to improve the GBW and thus speed of the comparators and replace the noise of the comparator with the better defined noise of the amplifier.  As a side effect there will be a reduced noise bandwidth / filtering of really high frequency noise. So also some of the noise from the LM301 could be reduced by limiting the bandwidth.

With amplification R215 and maybe R214 should get larger to.

Only at the very extremes (e.g.  more than 9.99 V in the 10 V range) the switching of the comparator might be relatively close the switching of the forcing signal and thus a delay from the amplifier could have a small negative effect on linearity. The longer the integration time, the less important this very last switching moment gets - so no real deal for 7 and 8 digit modes. Except just after switching the output of the integrator is a rather low slew rate (e.g. 300 V/s) signal. So the amplifier does not have to be really fast.

Using more modern comparators is tricky: most use lower supply. Also a faster comparator will be sensitive to higher frequency noise. So faster is not better in this respect. The only advantage might be from having a build in hysteresis instead of the added in AC feedback - but the test showed no big problem with this. After amplification I see not problem with using a LM311.

Another possible improvement could be RC filtering (e.g. 5K 1µ) at the reference (at pin 2 of IC305). This could reduce the 160 Hz band noise, though likely not a really big deal, unless the reference is really noisy.

[barnacle2k]

The data show something like 3-5 times the noise as the data from barnacle2k - assuming these data are measured without filtering.

The digital filter mode on the DMM was not active.

It might still be interesting to see a FFT of these data, especially the 6 digit mode, to see if they show the same correlation. It might be a little difficult to see, as the quantization noise is of similar size.

My data looks similar when put through an FFT.

[e61_phil]

Is there a simple but sufficient example for a foldback amplifier available anywhere?

[Mickle T.]

Datron 1271:

[Kleinstein]

I just realized that to little forcing should not be the problem: the 5 digit mode use a higher forcing frequency and thus slightly stronger forcing as the capacitor has lower impedance. So not much sense in doing a test with a little more forcing.

For the amplifier, one would need a non inverting version here, if the original comparators are used. I don't think the extra filtering shown in the plan above is needed in this case (rather low forcing frequency), so just an non inverting amplifier with the extra diodes in feedback should be enough.

The extra filter adjustment might be there to improve the step response a little, e.g. need for less delay during autozero mode, which is not that important with the solartron, as the drift is very low. As far as I see, the step response may not be really good for this ADC anyway.
 
One could use the inverting circuit if one also adds the comparators to the extra circuit.

[Mickle T.]

The 5 digit mode use the same 160 Hz forcing frequency.

[wiss]

I've measured the 160Hz signal in https://www.eevblog.com/forum/metrology/solartron-7071-7081-last-digit-is-jumping-all-over-the-place/msg885093/#msg885093
The variation was about 1000ppm.

Here you did synchronize to the functiongen and not a real 50 Hz line?

[e61_phil]

I've measured the 160Hz signal in https://www.eevblog.com/forum/metrology/solartron-7071-7081-last-digit-is-jumping-all-over-the-place/msg885093/#msg885093
The variation was about 1000ppm.

Here you did synchronize to the functiongen and not a real 50 Hz line?

The 160Hz was generated by the PLL in this measurement. My Siglent function gen might be bad, but not that bad

[wiss]

The 160Hz was generated by the PLL in this measurement. My Siglent function gen might be bad, but not that bad

Ok so then we assume that the +-2.5% variation in integration-time is due to LabView?
(that large line frequency variation will probably ruin larger (and smaller) motors and all kinds of bad stuff might happen...

[e61_phil]

The 160Hz was generated by the PLL in this measurement. My Siglent function gen might be bad, but not that bad

Ok so then we assume that the +-2.5% variation in integration-time is due to LabView?
(that large line frequency variation will probably ruin larger (and smaller) motors and all kinds of bad stuff might happen...

I don't think so. LabVIEW is normally stable within 1ms in my setup.

[e61_phil]

Today, I put a thermopile into the meter on top of the floating CPU. I'v measured 54°C at 23°C room temperature. Is that normal? I think it is quite hot.

Thanks for the fold amp schematics. I will think about a fold back amplifier with a gain of max 10 and a maximum output voltage similar to the maximum integrator signal on TP201.

[Mickle T.]

The normal temperature in my 7081 is about 50 C. deg. (in the middle of the analog PCBs).

[wiss]

The 160Hz was generated by the PLL in this measurement. My Siglent function gen might be bad, but not that bad

Ok so then we assume that the +-2.5% variation in integration-time is due to LabView?
(that large line frequency variation will probably ruin larger (and smaller) motors and all kinds of bad stuff might happen...

I don't think so. LabVIEW is normally stable within 1ms in my setup.

But, variations in integration time has to be below 0.25 ms, something has to be wrong here...

[e61_phil]

The 160Hz was generated by the PLL in this measurement. My Siglent function gen might be bad, but not that bad

Ok so then we assume that the +-2.5% variation in integration-time is due to LabView?
(that large line frequency variation will probably ruin larger (and smaller) motors and all kinds of bad stuff might happen...

I don't think so. LabVIEW is normally stable within 1ms in my setup.

But, variations in integration time has to be below 0.25 ms, something has to be wrong here...

Perhaps it has only todo with another data communication as mentioned earlier

A VCM signal would be really nice now

[wiss]

In the 7075 there is a tp for 50 hz sync, forcing, pll-out etc
Chech the stability on those with your oscope.

[e61_phil]

I posted already some of these measurements. None would explain these huge variance in the data acquisition time. I think that is due to internal communication between the CPUs or something like that.

[e61_phil]

Form the PDF linked above, one possible problem might be due to to little forcing signal - this might make the integrator plus PWM feedback part not getting fully stable. One could test this with something like a 10% more forcing (e.g. 390 K in parallel to R221). Other Solartrons even have a pot to adjust the forcing strength to find an good value - so maybe this one is just ad the edge.

390k in parallel to R221 changed nothing

[e61_phil]

@e61_phil:

Just curious...  Do you have the latest firmware in your DMM

-Ken

I dont't know. But the test with the digital part only looks fine.


I found this https://www.febo.com/pipermail/volt-nuts/2014-July/003430.html
Does anyone know Jean-Louis? It would be interesting if he could fix his problem.


Perhaps it is worth to also change IC201 against a LTC2057? That OP is a slightly slower but has very good noise specs.

On german ebay is an auction with a 7071. Unfortunately, this meter is also noisy. So no chance for cross checks.

[wiss]

I posted already some of these measurements. None would explain these huge variance in the data acquisition time. I think that is due to internal communication between the CPUs or something like that.

Oscope, trig on forcing, holdoff to whatever is lcd of 50 and 160 Hz, post sync and forcing with persistence.

Or I pick up the multimeter for 50 eur next time I come to de

[Kleinstein]

The question on the software version is a very good one. The is a possibility to reduce the observed type of noise by a kind of digital filtering, especially for the 7 and 8 digit modes. As this type of noise could be a principle weakness of the design, newer Version might use this.

IC201 is not expected to contribute much to the noise, and only the more white noise type. So it does not make very much sense to upgrade here. If you really want to, the more direct, upgrade should be a LTC1052.

The more promising candidate for an upgrade would be IC202, as this chip is expected to give a contribution of the right type of noise. For a test one could also just reduce the bandwidth of the existing LM301 by modifying the compensation (e.g. increase value of C204 by a factor of about 5). This is more of a test only as this could have a negative influence on linearity.

More promising would be the extra amplification between the integrator and the comparators - many modern DMMs use this trick to improve on the comparators. A limited bandwidth here would also reduce noise from IC202. This modification is expected to reduce a noise source of the observed type (mainly higher frequency).

A totally different point, might be looking at the supply. "noise" from the supply could influence the comparators, as the decoupling in this area is not very good, but hard to fix / improve. Even if not visible on the scope ripple on supplies could cause trouble and might be the difference between good and noisy meters.
One  source for supply noise are the switched mode regulators. So looking at there output caps or tests with added caps there might be worth a try.

[e61_phil]

I thought about the foldback amp and I think it is impossible to fold down to 1 with only one Opamp non-inverting without saturating anything if the amplifier should reach 10V at the output.

[Kleinstein]

The amplifier does not need to reach full range at output. The comparator don't need the full amplitude at all, but they also don't care much about 0.7 V more.  All you need is the range between the two comparators. So this is currently 0 V and something like 90 mV,  but I don't see a big problem making this range a little smaller.

So one could use just an non inverting amplifier and parallel the feedback resistor with 2 (or maybe 4) diodes. So close the zero amplification could be something like 10 and at larger voltages it's close to 1. R222 can than be adjusted (e.g. 22 K)  to have the second comparator at maybe -0.4 V instead of the old -90 mV.

[e61_phil]

I placed a fold amp (only breadboarded) into the meter, but no change in the noise

I also placed a new cap in parallel to the old one in the 5V switching supply for the floating electronics.

It seems that there is relativley high frequency noise (10th of kHz) in the circuit which produce some jitter on the comparators.

[Mickle T.]

I think it is possible to cut the +5V raill from the Floating Power Supply and connect it to external linear one.
Or add a capacitors in parallel with C55 or D53.

[classicTEK]

Hello All,

I have read in this string about the problems of instability of the LSD.  I may have missed it in all of the very detailed things that were tried already, but did this meter act this way BEFORE you removed the jumper @ LK17?  The only reason I ask is that I just picked one up that is in exceptional condition with factory Schlumberger calibration stickers still intact.  She seems very stable so far as a GREAT 7071.  Should I expect similar degradation of the stability of the LSD if I too remove the jumper?

Cheers,

David

[Kleinstein]

AFAIK the jumper only changes the number of digits displayed, so a kind of choice in software version. It can always be undone.
With less digits displayed, one would not easily see the higher than normal noise, even it is there. So the changed jumper only makes it (more) visible, but it should not influence the noise itself.


For the switched mode supply one should also look at ripple on the input side. A high ESR for C51 could send ripple all the way back through the transformer. An extra cap (e.g. a few 100 nF) at the AC side might be an idea. The same is possible with the earth connected supply.

One could also check the switching waveform (e.g. emitter of TR52) if this looks good. Just to see if it about improving filtering of the normal ripple or maybe an not well working switching transistor (e.g ringing there - so a snubber or changed transistor  would be more appropriate).

[e61_phil]

I can't say if it changed with removing the jumper the first time, I don't think so. I read stories about one of the DIP switches for the GPIB adress where used to switch between 7071 and 7081 during the design of the meter. Everything inside my 7071 is labeled with 7081 (including the stickers on the EPROMS) so I think there is really no difference excpect the frontpanel and the selection of the reference diode.

[e61_phil]

Hello All,

I have read in this string about the problems of instability of the LSD.  I may have missed it in all of the very detailed things that were tried already, but did this meter act this way BEFORE you removed the jumper @ LK17?  The only reason I ask is that I just picked one up that is in exceptional condition with factory Schlumberger calibration stickers still intact.  She seems very stable so far as a GREAT 7071.  Should I expect similar degradation of the stability of the LSD if I too remove the jumper?

Cheers,

David

Hi David,

is it possible to do some measurements in TEST0 mode or in 10V mode with a short at the input? It would be very interesting how much noise a good 7071 will produce.

Thx Philipp

[bertik]

Hello,  I have a similar plus also a worse problem with my 7081.
There are two symptoms:

1) Noise level is more or less the same as described here. At 7 digit resolution it matches the same noise level as of a new Rigol 3068 at 6 digits, 100NPL. From what I gathered here, it may even be within specs. But this is not the main problem.

2) The main problem is a sudden drop in the reading after a few minutes of warmup. This is 100% reproducible. This occurs for all measurements and already in the 10V range. There is sudden approx 80uV drop whenever the temperature crosses a certain line. By fine tuning I even got it to oscillate. I will post pics below. White trace is Rigol 3068 and red trace Solartron 7081.


I spend hours on this, to no avail. What I tried was:

a) Monitoring all sorts of PS voltages in sync with the drop - no correlation seen.

b) Exchanging IC201.

c) Using cold spray selectively on all sorts of locations, nothing systematic

d) checking the PLL voltage (2.5V) whether it jumps in sync - no correlation seen.

e) checking +/- 10V reference voltages, whether they jump in sync - no correlation seen.

f) substituting a VRE102CA voltage reference in lieu of Z-diode, but jumps continue to occur. If at a later stage this works better than the built-in Zener, I may keep it there.


3) Then there is a mysterius property which seems unrelated but puzzles me.
Probably it is a trivial mistake on my side, but so far I couldn't figure it out (without disassembling the board). It is about TP305, supposedly 0V in the reference section. It is located on the PCB between IC304 and IC307.

I measure 15Vrms 50Hz sinoidal AC between this and the 0V point TP505!  TP505 itself has perfectly stable +/- 10V ref against the positive and negative reference points, TP302 and TP303. But TP 305 is per schematics the proper 0V point, and carries this high AC voltage. How come?  When powered off, I measure like 2Ohms between TP305 and TP505. This doesn't make any sense to me - it appears like a transformer winding, low Ohms but a lot of AC (??)

Perhaps someone can enlighten me...  and also give a tip about what to do against this voltage jump.

Thanks!!

[Kleinstein]

The 15 V AC at TP305 is strange. Is it possible the meter is in ratio mode ?
This might couple something else to this point.
This AC voltage might cause trouble with the ADC for current setting to the reference and thus cause the jump. So it is like a wonder anything works with this.

The solartron7081 is known to be relatively noisy. I don't really know what the noise source is.
Much of the noise is correlated between adjacent readings - so longer integration time really helps. This also points towards things like "noise" coupled from the switched mode supplies as an important noise source. Though there might be still quite some noise from the reference diode.

Is the 80 µV jump also appearing with a short input, or just when measuring 10 V or similar ? So it an additive jump or a change in scale factor ? The voltage at TP301 might be interesting too - as opto-couplers are somewhat prone to aging and might react to temperature.

[bertik]

Thanks for quick answer. I will check ratio mode but don't think it is. But the optocoupler is a good idea, I didn't think about it yet.

Actually there is a pre-history, a few years back: I had to exchange a couple of them (ILQ74 or so) before, since the whole instrument stopped working after a few minutes. There were thermal failures all over.

I will check and get back,
thanks!

[ManateeMafia]

Doesn't the 7081 perform an internal cal every 15 minutes or so? I thought there was mention of it on the volt nuts mailing group. There was a bug in the firmware that was fixed by one of the members. It would add an offset to the measured value. I think it was Mickle T.

If you haven't downloaded his notes from ko4bb, I would recommend looking them over. There is a lot of good info in the large download.

Edit: Added chart showing AutoZero bug from ko4bb download.

[bertik]

Hello, thanks for your answers!

Is the 80 µV jump also appearing with a short input, or just when measuring 10 V or similar ? So it an additive jump or a change in scale factor ? The voltage at TP301 might be interesting too - as opto-couplers are somewhat prone to aging and might react to temperature.

At 5V the jump is like 40uV, and in the 1V range at 1V it is about 8uV and no jump for short circuit, so it is proportional to the voltage. Sounds like reference voltage but surely this isn't the cause..

At TP 301 there is no jump or anything peculiar seen when the reading jumps.

Doesn't the 7081 perform an internal cal every 15 minutes or so? I thought there was mention of it on the volt nuts mailing group. There was a bug in the firmware that was fixed by one of the members. It would add an offset to the measured value. I think it was Mickle T.

Yes I downloaded this great collection of data and am trying to sift through. Thanks for pointing out!
 
The chart you posted is most interesting, especially the error is of the order of the jump I see. The jump however is generically not periodic and happens always at about the same temperature (I track the temperature by comparing the offset against another DMM. The offset decreases at a given rate over time, depending on whether the case is closed or open, room temp, etc.).

Nevertheless it could be due to combination of factors, one of which is autozero. What I can try is to re-establish, by fine-tuning, a periodic pattern and see what the period is - if it would be about 15min, it would tell something!

I had expected to locate any temperature sensitivity by a cooling spray but never could pinpoint it. Of course some components are sensitive, like the chopper amp IC201, but exchanging that didn't have any influence. So if this is indeed software related then no wonder!

Thanks!

[Kleinstein]

If I understand the problem with the AZ bug right. It is very well possible that this could explain the trouble:
looks like they don't wait long enough for the ADC / amplifier to settle to the 0 value and this way add an error in the AZ measurement, about proportional to the measured voltage.

I would guess one could start the AZ phase also manually or in software - so it should be reasonable easy to check. Though one would only see a difference if the instrument has actually drifted or changes the measured voltage since the last Adjustment otherwise the wrong offset would just persist.

[bertik]

Today, I burned the IC803 Eprom with the patch v1.1 of the ko4bb download. Alas, the problem persists.

But here is an interesting observation: I checked the data files I had collected over time and indeed, the jump occurs always in the order of 15min!  See the attached plot of today, with the patch applied. Horizontal unit is 10s per bin, makes about 800s,  gives 13min...and .there was a bit time before the data were taken. So indeed it looks as if it is somehow related to the AZ.

Edit: of course it may be that it just coincidentally, a certain temperature is always reached after ~15min given constant ambient temp. I will run the whole test overnight at low temp to distentangle time vs temperature, once for all.

Edit2:
I added a plot where I re-initialized a few times the 7081 a few moments after a drop. As one can see, the value before the drop is resumed, until the next drop happens. The drops appear typically around 15min after but not precisely, there are variations. I can hear some relays click after 15min, and assume that this is due to AZ. However, I didn't observe any coinicident jump. Moreover, as you see there was a drop to zero which was remedied by itself, and in the end the whole thing crashed and got stuck at output zero.

So there seems to be a circumstantial evidence that AZ is involved but the timing is not 100% accurate.

I feel about giving up  --  if the single jump after ~15min is 100% reproducible, as it looks, it can be taken into account with the calibration (which is messed up anyway). From the various thermal defects I encountered so far the 7081 must have has a pretty hot pre-history..

Thanks for all!

[ManateeMafia]

Send Mickle T a PM with a link to this thread. He has a pretty good understanding of this meter, maybe he can help diagnose your issue?

[Mickle T.]

I think there is an odd thing with AZ, but I can't understand what is

[Kleinstein]

My guess is, that at the about 15 min intervals there is more going on than just auto zero. It could also include gain adjustments. At least even with AZ off, there are still things happening at those intervals.
If there is an adjustment, I would expect a break, with no new data coming in.

The spikes somewhat suggest that it takes longer than planed to recover from these adjustment measurements.

[bertik]

Hi Mickle, 

thanks for chiming in.  The plots that you show, are they as they are supposed to be, or pathological?

 To me they seem to make some sense, a periodic adjustment until the whole thing has stabilized. On the other hand, for precision measurements I'd expect a somehat less bumpy behaviour ;-)

My S7081 shows similar behavior after the first jump. Attached is another, long term plot where the red trace is from a Rigol 3068 at 6 1/2 digits, the blue is for the ailing S7081 at 7 1/2 digits. Clearly even after the jump not really a high-precision behavior....

[3roomlab]

3 things come to mind when i see your log having little ticks. when the AZ switches on/off, the shift of "reference" must be measuring part A of circuit then it go to part B, i am thinking maybe the common ground is not on same level? and small 0.2- 0.3ohm difference in 2 parts of the PCB create small difference (this problem appeared in my old K2015, i bridged all major sections with a 1.5mm, K2015 power traces are tiny)? 2nd is maybe bypass capacitors no longer working well? when certain circuit turns on and the draw create a dip (i am purely randomly guessing this 1)? 3rd : can the time base of AZ be changed/hacked to smaller period? ... or the most remote of all suggestions, what if you create an external clock to trick it to do a faster AZ period? --> i have no idea how the solartron works ! so this is likely way off at planet jupiter !

[Mickle T.]

The plots that I show, are Ok.

[Kleinstein]

It looks like the plots are for 3 different meters. So it is a little hard to compare the effect of have AZ on and AZ off. The main conclusion is that the glitches are a common thing, with an without AZ active.

I am a little confused, as there is a way to do AZ with the input amplifier includes and one without it (e.g. only the ADC). I would expect to the AZ including the input amplifier, though the chopper stabilized amplifier might not drift very much - though not that much drift is expected for the ADC too. So I am wondering how much of the adjustment steps is due to gain and AZ adjustments.

I am just wondering which part of the circuit is responsible for the glitches just after the AZ / adjustment phases. Is this the input amplifier (e.g. chopper stabilization), the dielectric relaxation in the integrating capacitor or something else.

The input amplifier looks a little strange in three aspects:
1) They use a BJT pair for the copper part amplification instead of JFETs.
2) use of OP05 as an AC amplifier - could be already limited by GBW.
3) Cross over from the direct path to the chopper path seems to be at rather low frequency
But I can not see an obvious reason for slow response to to large signal steps. At least one be able to  test this independently.

[Mickle T.]

Well, a few words in support of AZ 
1. Drift correction includes only ADC zero and did not touch a full scale constants or an Input Amplifier.
2. If drift correction is disabled via the terminal command "drift off", there is no any glitches in the measurement results. In other words, in known working condition the Solartron 7081 have no any other sources of glitches.
3. The main (input) amplifier is very stable and "silent", and does not require any seft/auto/e.t.c. corrections. The noise floor in 1:1 configuration and short input, measured by N1a nanovoltmeter, is 10...20 nV p-p (DC-1 Hz).
4. It is possible to change AZ interval by swapping one byte in the Parsing_7F procedure. But I think it makes no sense.

[Kleinstein]

I very much doubt the input amplifier could reach 20 nV_pp level, even an 20 nV/sqrt(Hz) would be on the low side.

Already the two 15 K filter resistors should give about 22 nV/sqrt(Hz) of unavoidable noise. An BJT amplifier following this should about double the noise power (3 dB NF is already good for BJT). So likely more than 30 nV/Sqrt(Hz). And thus maybe a 200 nV_pp noise range, if there are no large other noise sources. This would be still a good value.

Changing the rate of AZ measurements does not make that much sense. It might be a good idea to increase the delay for the ADC to settle, when changing from normal measurement to the zero measurement. The glitches somewhat suggest that it takes some time for the ADC to settle to its final value. The source could be DA in the integrating capacitor.
Thus too fast a measurement would introduce a small error. One cold test for this by doing and Zero compensation with a high input voltage applied (e.g. 10 V) before, than switch to a shorted input and after something like 1 min do a zero adjustment again. The jump during that last zero adjustment should show the error from the first adjustment (plus some drift).

In principle there could be constants to correct for the fraction carried over from earlier readings.

[bertik]

The source could be DA in the integrating capacitor.
Thus too fast a measurement would introduce a small error. One cold test for this by doing and Zero compensation with a high input voltage applied (e.g. 10 V) before, than switch to a shorted input and after something like 1 min do a zero adjustment again. The jump during that last zero adjustment should show the error from the first adjustment (plus some drift).

This is exactly what is happening: after a large voltage change (esp. switch-on), the next AZ (also when manually triggered) creates the jump of 80uV or so, the subsequent ones are fine!  So this is coming closer to a resolution.

I exchanged the 0.1u integrating cap C201 with a MKP for the time being, there was no change however. Also the noise stayed as before. But at any rate, I am expecting a high precision 0.5% Polystyrene cap and will put it in  and see what happens.

This was really helpful and is highy appreciated, thanks!

Bertik

[Kleinstein]

The integrating cap is already specified as MKP. So changing to another MKP is not changing much. I am not sure than polystyrene is really better in that respect.  There is no need for high precision with that cap - 10% tolerance would still be OK.

For the noise it might be interesting to check for the type of noise, by looking at correlations in subsequent readings. The analysis earlier in this thread suggested that much of the noise (in the 6 digit mode) comes from the start and end of integration, so the first and last comparator readings. The nice thing about this type of noise is that it goes down linear in integration time and not just with the square root as white noise would do. So noise should go down with increasing integration time relatively fast. This also applies to taking data and average later on.

I suspect noise from the power supply could be a factor, as the noise is higher than what is expected from the circuit diagram.

[bertik]

Here is a brief update. Excerpt of my blog .

While investigating there was a serious setback: when checking the current setting for the reference Zener, I inadvertently shorted the test pin 301 with the – input of IC 304 (refers to service manual). There was a sense of smoke, which was surprising, since this test pin is supposedly at ground. I checked and alas, there was 17V AC voltage at it! With source impedance of like 2 Ohm… how could this possibly be? Was it the effect of the short? How can 17V AC go straight into the reference voltage section?

After disassembly it turned out that the test pin was wrongly placed by the manufacturer, namely on a via. And indeed there is 17V AC voltage there, fed across half of the board to a few mm near the reference section (!). It enters IC303 which is close by. So that explained it. As a consequence, IC 301 and IC 303 where blown and possibly more.

I decided to by-pass this problem by substituting an (aged!) +10V/-10V precision reference VRE102CA of which I had salvaged a few from trash. It can be made fit perfectly into the reference section of the 7081, by attaching the outputs to the reference terminals TP 302/TP 303 and opening the base and collector connections of TR 301 and TR 302. This works as good as before, the reference has like 1ppm/C temperature stability and like 3uV pp noise 0.1-10Hz.

Incidentally, does anybody know what the corresponding specs are for the 7081 Zener?

For the time being I’ll leave the reference section like that, since the excessive noise problem is the next pressing one. I will report on any progress in the future.

[Kleinstein]

The good thing is that chances are good that only IC301 and IC304 (741 OP) are blown and there should be replacement for the DAC available. This part is only for selecting the exact current for minimal TC. Even a direct replacement could influence calibration a little. Worst case, or for a first test one could replace that circuit part (optocouplers, DAC and OP) with a trim pot.

A 3 µV_pp noise spec is actually quite good - depending on the frequency range.
The LTZ1000 is specified at 1.8 µV_pp typ (3 µV max) if scaled to 10 V.

With the noise specs of the zeners, there is not much data and the value scatters a lot. The nominal value can be quite poor, but good instruments usually use selected ones. So even if one has a data-sheet that gives typical noise figures this is of limited use.  It would likely be more useful to actually measure the zener's noise.

Reference noise is not that important for the noise with a shortet input. In this case one the noise densitiy in the 160 Hz (forcing signal) range should enter. If one really wants one could filter this.

[bertik]

Thanks for your answers!

The good thing is that chances are good that only IC301 and IC304 (741 OP) are blown and there should be replacement for the DAC available. This part is only for selecting the exact current for minimal TC. Even a direct replacement could influence calibration a little. Worst case, or for a first test one could replace that circuit part (optocouplers, DAC and OP) with a trim pot.

The smoke actually came from the resistor array R302 feeding into the optocoupler IC303.
Despite a burn mark, the resistors are still fine. But the driving IC 830 might have been damaged as well, I didnt yet fully check. All the chips are easily available, so far I just replaced the 741. But it is a pain to replace IC's, when PCB traces tend to peel off etc.

Thus indeed the trim pot is a good idea. All what the DAC plus periphery is doing is to supply a programmable voltage resp current into the Zener. From the setup procedure sheet a numerical code "064" corresponds to zero and "124" to -9.18V (why not 128??) at TP301.  From the originall NVRAM settings I know the stored value was "104". Thus it is an easy exercise to compute the necessary voltage.

A 3 µV_pp noise spec is actually quite good - depending on the frequency range.
The LTZ1000 is specified at 1.8 µV_pp typ (3 µV max) if scaled to 10 V.

Normally the VRE102CA are spec'd to 6uVpp.  I measured a few of them, and they went from below 3uV to 5uV plus a stinker with 30uV+. Two in parallel went down to 1.9uVpp at 10V. See attachement (100mV corresponds to 1uV input).  For this the DIY low noise amplifier of the other thread was very useful.

With the noise specs of the zeners, there is not much data and the value scatters a lot. The nominal value can be quite poor, but good instruments usually use selected ones. So even if one has a data-sheet that gives typical noise figures this is of limited use.  It would likely be more useful to actually measure the zener's noise.

I may give this a try, which is a challenge in the noisy environment of the DMM.

[Mickle T.]

Selected 1N829 with R305 & R306 dividers provide a 6.4 ppm/y of long-term stability of the S7081. Guaranteed!
VRE102CA have a much worse specs, so downgrades a S7081 perfomance to HP 34401A level.

[acbern]

My 7081 is showing stability (drift) issues as well, maybe this also sheds some light on the original issue that was brought up here (and not resolved).
I traced my issue down to an input leakage current, which causes a voltage drop accross the protection resistors R5 and R6 at the input. The leakage varies, so does the voltage drop and hence the voltage read. It is about 25mV too low (10V input). I removed D101 and C103, so these can be eliminated as a cause.
So seems the input amplifier has a leakage issue. So my thoughts are it could be TR401, less so TR412. Since I have not found these, hard to just replace them.
Would not think TR406 to 409. What would the Solartron experts here think, anything else? D401/408?
And what replacement part could be used for TR401? Dont find the original or its data sheet anywhere. Maybe IFN401/U401? None of the parts btw. are cold-spray sensitive.
Any other thoughts?

[Kleinstein]

The not really solved original problem is something at the ADC itself: Somehow influencing the single comparator triggering time and thus the error of readings in sequence is anti correlated. Leakage / drift of the input amplifier is a completely different thing.

How large is the leakage current about ? One could measure it with something like 1 M or 10 M at the input.

There are quite a few parts that could contribute to leakage. It might be possible to separate the chopper part by unsoldering R407/R408 and maybe R406. This would isolate possible leakage and variations in charge injection from that area.

[e61_phil]

The not really solved original problem is something at the ADC itself:

My meter is still waiting to be fixed, but I have to finish my phd thesis first.

Drift was fine, noise is my problem.

@acbern: Where do you come from? Perhaps it can help to swap parts between the meters.

[acbern]

Thanks for the hint re. chopper isolation. Charge injection could be an issue, and I have not thought about that yet.
I had tested the input resistance, it varied, some ball park was 10 meg., it varied, hence the input drift.

The problem I have with stability in principle is acutally similar to the one e61_phil has, at a higher level. I have read somewhere on voltnuts someone had an issue with a protection diode in the input, causing noise/leaks, and mine could be just more leaking, just at a much higher level.
As far as parts are concerend, I think the IFN401 is a good bet, and re. input low leak protection diodes, the PN4117A jfet seems a good solution, so I may try this. Any opinions?

e61-phil: I am in the Munich area. Not sure swapping (at this stage) is the best for both of us, these are rare parts, mine may be broken, while yours at least are only a little noisy. Thanks, I may come back.
Still trying to find parts. The ones I mentioned should be ok, other suggestions wellcome.

[Kleinstein]

The protection diodes at the input only see a very low voltage ( < 100 µV) - so a normal low leakage diode like BAV199 should be well good enough. The circuit might not like too much light.

I would be very careful without those diodes, as I don't see an other ESD protection.

For the input current one usually measures the voltage reading with something like an 1M resistor - so the result would be a measured voltage or current.
The alternative test is a low leakage capacitor in the 1-10 nF range, and than watch the capacitor charge discharge - this way one can get the input current at different voltage levels too.

Before changing the rather expensive input FETs, I would check other parts first. One would be the drain voltage of the input FETs - in case the transistor array failed. For a first test one could get away with two single JFETs. At first glance the data for the IFN401 don't look that special (except rather low capacitance which should not be critical here). DC performance is set by the chopper part anyway.

As far as I understood the meter, there is an option to test the ADC without the input amplifier.

[e61_phil]

For the input current one usually measures the voltage reading with something like an 1M resistor - so the result would be a measured voltage or current.
The alternative test is a low leakage capacitor in the 1-10 nF range, and than watch the capacitor charge discharge - this way one can get the input current at different voltage levels too.

My method to measure input current at different voltage levels was simply to connect a high resistance (10G for example) in series to a calibrator. With this setup one can calculate the drop over the resistor and accordingly the current.

[acbern]

For the input current one usually measures the voltage reading with something like an 1M resistor - so the result would be a measured voltage or current.
The alternative test is a low leakage capacitor in the 1-10 nF range, and than watch the capacitor charge discharge - this way one can get the input current at different voltage levels too.

My method to measure input current at different voltage levels was simply to connect a high resistance (10G for example) in series to a calibrator. With this setup one can calculate the drop over the resistor and accordingly the current.

I did that, using an external resistor (1M), and also did that using just the internal 2x18k protection resistors. Same results re. leakage current/input resistance (again, it anyway fluctuated). It also matched the input resistance measured with a simple meter. Since the input resistance was so low (10M range), I didn't even have to go to a capacitor to test it.

[wiss]

What voltage range are you in? 10 M is way low for the lower ranges.

[Kleinstein]

A 10 M resistance would point to something like the high voltage divider always active - so it could be a hanging relay. For the higher voltage ranges (> 20 V) the 10 M input resistance is normal and so is some extra noise. to really test the input amplifier noise  one should use the 100 mV range and for the input bias the 10 V range might be more suitable (to test at higher voltage).

[acbern]

The range I was focussed on was 10V. Therefore the roughly 10M is really a leak issue (it is not the 10M input divider that is on by mistake, and the leakage was even lower than that). I found this when measuring the input voltage and the voltage inside after the 2x 18k. There was a considerable voltage drop accross these two resistors, and drifting. Actually, the input resistance started at about 1M, but is now up at about 10M.
I have eliminated D101, C103, have decoupled the chopper (R406, 407, 408 removed). The voltage changes a bit of course then, but the high leakage and slow drift is still there, so its not the chopper.
I am thinking this only leaves D401, D408, TR401 (and TR412). D401 and 408 are in plastic TO92 case, so I would think photo current is not an issue, and leakage (forward and reverse) are probably neither, since the voltage accross them is low. Still, as its easier, these are the next candidates. And then TR401.
Any thoughts?

[Kleinstein]

One cannot measure leakage current in MOhms - it should be nA or pA !

When removing the chopper part, some drift is normal. If the voltage did not change much when disabling the chopper part, it could be that the chopper part did not work all the time. Also still having a similar drift points towards a problem with the chopper part. Either because the chopper part is broken, or the offset of the normal amplifier got too large.
With to much voltage (e.g. 10 mV range) at the chopper part this might look like leakage. As the copper can have a relatively low (e.g. 2 M) impedance between it's inputs. This is normally not a problem because the voltage is essentially zero if the chopper is working correctly.

So how much offset was there with and without the chopper part active ?

[acbern]

One cannot measure leakage current in MOhms - it should be nA or pA !

That is obvious, but I did not say this.

When removing the chopper part, some drift is normal. If the voltage did not change much when disabling the chopper part, it could be that the chopper part did not work all the time. Also still having a similar drift points towards a problem with the chopper part. Either because the chopper part is broken, or the offset of the normal amplifier got too large.
With to much voltage (e.g. 10 mV range) at the chopper part this might look like leakage. As the copper can have a relatively low (e.g. 2 M) impedance between it's inputs. This is normally not a problem because the voltage is essentially zero if the chopper is working correctly.

So how much offset was there with and without the chopper part active ?

The chopper was totally isolated. All three resistors were removed, so chopper disconnected. The change in voltage displayed was minimal, in the 20mV range, expectable range. In that state, with essentially TR401, IC401 and 402 remaining as a differential amplifier, there should have been no leakage current at all. I do not see a rationale why in that state the disconneted chopper should cause an input leakage current (with sligtly varying value, causing a drifty reading, caused by a voltage drop accross R5 and 6, in the 5mV range), when disconnected. The input only sees FET gates arround the Input Amp and the two antiparallel diodes. Still there is a high leakage current flowing. That is definitely wrong (may not be the only issue). RL7/4 also in the path, and not eliminated yet as cause, but not that likely for leakage, but still tbc.
Also, with the chopper connected, the small changes in the mV range at the TP403 chopper demodulator output (which was at about 2V) were not correlated to changes in the diff amp input voltage/meter reading. The chopper may still have an issue, beyond whats going on with the FETs/diodes, but the 2V output at TP403 does not look wrong at a first glance.

[Kleinstein]

2 V at TP403 sounds reasonable, especially if there is some movement too. So chances are the chopper could work and the problem is in deed leakage. Of cause the copper can not cause leakage when disconnected - it was not clear that there was still leakage with the copper disconnected. There was just not much information on how much leakage / offset problem was there before and after disconnecting the chopper.

When the output without the chopper is only changing by about 20 mV this indicates the normal differential amplifier is also still working relatively good. It could still show some drift - even with JFET pairs drift in the 10-50 µV/K range is normal.

5 mV at the 36 K input protection resistors would be a leakage current in the 100 nA range, so definitely too much, and more than one should expect from a dirty board.

The easy part to test would be probably the protection diodes. For a first test even 1N4148 should be much better than 100 nA. Ane could also use base-colector junctions of small transistors (like Bc547) as low leakage diodes.
This would mainly leave TR401 and TR412 as the possible leakage paths.
IC401 could contribute indirectly: if broken the voltage at TR401 drain could be too high - worth a test as there are quite some reports of those CA3xxx transistor arrays to go bad (for no good reason).

One could check the function of TR412, by looking at its offset.

[perdrix]

Did anyone ever reach any conclusions on how to fix or at least mitigate this problem (apart from turning on the Digital Filter)?

Thanks
Dave

[Kleinstein]

Did anyone ever reach any conclusions on how to fix or at least mitigate this problem (apart from turning on the Digital Filter)?

Thanks
Dave

There are several problems describes in this thread: One is ADC noise, a second a not so well working AZ function and at last a broken input amplifier.

The relatively high noise is a known property of this meter. Form the correlation of the samples it looks like a higher frequency noise effecting the first / last comparator reading and is thus not adding up. So it gets better over time. It does not seem to be the LM311 and the noise seems to be higher than expected from the circuit. So it's more like a problem with supply noise or similar.

The AZ problem is more like a principle problem - that might be partially corrected with a software update. But it also has a root cause in the type of ADC with a large integrating cap that changes voltage quite a bit. So there is some effect of dielectric absorption - so there might not be a really good solution except a different type of ADC. This could kind a limit to this type of ADC.

[pigrew]

I'm in the process of restoring an abused 7081 at the moment. Based on the above discussion, autozero seems to be a major issue with these meters. I've not yet turned on my unit (it had some bulging capacitors, among other things. I'll create a repair post at some point.).

The AZ problem is more like a principle problem - that might be partially corrected with a software update. But it also has a root cause in the type of ADC with a large integrating cap that changes voltage quite a bit. So there is some effect of dielectric absorption - so there might not be a really good solution except a different type of ADC. This could kind a limit to this type of ADC.

I noticed that the download package from xdevs/ko4bb has tweaked firmware which extends the autozero pre-delay time (both a version 1.0 and 1.1). Is it generally suggested to install the tweaked firmware?

[borghese]

Hello
My 7071 jump 3 digits in 7x9.
It is known that the 10.48576 MHz oscillator, in the floating logic, for synchronisation with the main supply is not very stable; if you have a stable signal generator, you can disable TR805 and inject the signal on TR806 base.
I think Mikle T. has already done this
I have not read all the posts; my apologies if anyone has already suggested this.

[tggzzz]

Hello
My 7071 jump 3 digits in 7x9.
It is known that the 10.48576 MHz oscillator, in the floating logic, for synchronisation with the main supply is not very stable; if you have a stable signal generator, you can disable TR805 and inject the signal on TR806 base.
I think MikeT has already done this
I have not read all the posts; my apologies if anyone has already suggested this.

It should lock to whatever the mains frequency happens to be at the moment. When I got my 7081, it didn't.

Ensure you have the right division ratio for the 50/60Hz, and, if necessary, tweak the trimpot 6-30pF C807 near the varactor.

After tweaking there was a significant improvement.

[branadic]

What is the reason that the oscillator is instable? If it's due to temperature one can use a  crystal heater to stabilize it. All you need is some voltage between 8-12V for it.

-branadic-

[e61_phil]

It is due to the instability of the mains frequency. There is no crystal. It is a PLL which is locked to the mains frequency.

[tggzzz]

What is the reason that the oscillator is instable? If it's due to temperature one can use a  crystal heater to stabilize it. All you need is some voltage between 8-12V for it.

It is locked to the mains frequency to reduce some noise/interference effects. That's why you sometimes see people specifying high resolution measurement time in terms of NPLC, number power line cycles.