1. The "ID" bits in GENDiv and GENCTRL refer to the Clock i am configuring except in CLKCTRL it refers to the final output peripheral , with the exception of DFLL48 to loop back around...
The question is not clear. In both cases they refer to GCLK Generator ID (value 0-7). It is basically the same thing as if there were 8 sets of registers (which would be better, IMO).
2. In the last function the code does not specify an "output" ID in CLKCTRL ? so generick clock 0 in this case is the one with 48mhz output...?
It sure doses. You are making GCLK0 output 48MHz taken from DFLL.
3. Does it have to be Generick CLock 0?
It can be any GCLK you like.
4. To apply this 48mhz to a peripheral would i configure a generick clock with generator 0 as the source? or DFll48?
You do something like this:
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(TC0_GCLK_ID) | GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0);
This enables clock for TC0 (and TC1, since all timers are doubled up).
Basically in a peripheral you specify GCLK1 that you configured previously.
5.and why is the PORT not an option in the ID section for CLKCTRL
Ports are always clocked, I guess, but I'm not sure with what clock. More reading of the DS is required.
Also what does coarse and fine step do to the DFLL?
Coarse is used to get initial lock and then frequency is fine tuned with fine steps.