What's the point in DDR?

[Boscoe]

I've always found the objective of lowering the clock speed while maintaining the data rate strange. Who cares for having just one of your 40 signals of your RAM going at half the bandwidth as the rest? The 8/16/32/64 bits of data is still running at twice the clock rate. It doesn't seem to have any significant benefit to me and only makes clocking more of a hassle in logic.

What am I missing?

[langwadt]

I've always found the objective of lowering the clock speed while maintaining the data rate strange. Who cares for having just one of your 40 signals of your RAM going at half the bandwidth as the rest? The 8/16/32/64 bits of data is still running at twice the clock rate. It doesn't seem to have any significant benefit to me and only makes clocking more of a hassle in logic.

What am I missing?

with ddr clock and data is at the same rate

[Boscoe]

That's true, I hadn't thought it through properly. Still, is it worth it?

[mikeselectricstuff]

Transmission line effects. the rising edge and falling edges both need to propagate and do any ringing, settling down etc. before the next transition. With DDR you send data on each transition, so for a given settling time, you get twice as much data
 

[cyr]

For DDR RAM, only the data and associated strobe signals run at DDR.

Think of it as doubling the transfer rate without having to increase the speed of the clock or the address/control lines (which typically have more load because they go to all RAM chips).

[NorthGuy]

That's true, I hadn't thought it through properly. Still, is it worth it?

There's maximum pulse width you can handle. Say, it is 1ns. This dictates the maximum clock rate - 500MHz for 1 ns pulses. If you use SDR, you use 2 ns pulses for data and the best you can do is 500Mb/s. But with DDR you use 1 ns pulses, which gives you 1Gs/s. Is it worth it?

[Berni]

There is also the benefit of the driving logic inside the chips. Typically DDR is implemented by simply copy pasting the input logic, but inverting the clock on one of them. That way the logic inside also runs at the same clock speed as before yet it can get twice as much data trough the same pins as one half is handling the rising edge and other the falling edge data.

Similar is done on the transmit side. There can be two copies of the data pin driving logic while the clock line drives a MUX that ping pongs between the two, showing the output of one on the high state of the clock and the output of the other on the low state.

[David Hess]

Think of it instead as using both edges of a single clock signal instead of using a 180 degree biphase clock which would require two clock lines.

[langwadt]

Think of it instead as using both edges of a single clock signal instead of using a 180 degree biphase clock which would require two clock lines.

it does anyway since the clk is differential

[David Hess]

Think of it instead as using both edges of a single clock signal instead of using a 180 degree biphase clock which would require two clock lines.

it does anyway since the clk is differential

But that is not how the differential clock lines are being used.  Internally after a differential receiver which rejects common mode noise, either positive and negative edge flip-flops or latches are used or the clock signal is converted to a biphase clock.  Toggling one of the external differential clock lines does not toggle half of the flip-flops or latches; externally it is just one differential clock and not two single ended biphase clocks.

[NorthGuy]

it does anyway since the clk is differential

A differential line uses two wires, but it is still one line.

[Berni]

The reason behind differential pairs is mostly to get around the pesky parasitic effects of PCBs

Toggling a diff pair doesn't send any common mode current into the ground while keeping all currents that are part of the signal tightly against each other to couple them. This makes the pair capable of carrying very fast signals over a long distance without degrading them. But the fact that they reject common mode interference on the receiving end is also a very useful thing because the ground plane in the PCB might ring about at 100mV or more in these very high speed digital systems.

[langwadt]

Think of it instead as using both edges of a single clock signal instead of using a 180 degree biphase clock which would require two clock lines.

it does anyway since the clk is differential

But that is not how the differential clock lines are being used.  Internally after a differential receiver which rejects common mode noise, either positive and negative edge flip-flops or latches are used or the clock signal is converted to a biphase clock.  Toggling one of the external differential clock lines does not toggle half of the flip-flops or latches; externally it is just one differential clock and not two single ended biphase clocks.

I know how it works, the point was that one differential and two single ended clocks require the same number of wires