I've devised an approach to throw out for comments. It goes like this.
1) A digital attenuator front end controlled by a uC.
2) A trigger comparator (ADCMP58x) next, feeding a 5ps stepping digital delay chip (sy8927u?, 2ns min delay, 7 ns max)
3) A 2.5 ns delay line (about 15" of 50 ohm FR4 microstrip, maybe U shaped) going to item 4.
4) A peak detect (ADCMP58x) comparator 'sampler' with a flash 8 bit DAC resistor R-2R ladder Vref. driven by a uC & the nearby (<1") delay chip signal from (2).
Ok, the 8 bit DAC R-2R ladder is configured in 'reverse' where the delay chip pulse feeds the top via a current limiting resistor and the uC either floats or grounds the 'legs' for the R-2R DAC to establish a Vref tapped just after the current limit resistor fed by the delay line. This effectively becomes the 'sampling pulse' for the 2nd comparator.
The duration of the sampling 'pulse' from the delay chip can be controlled by a TDR grounded leg cancelling reflection and by the hysteresis of the first comparator to a suitable period.
The basic operation goes like this.
The uC steps the dig. RF attenuator and the Vref of comparator #1 (a regular R-2R 8 bit affair) to obtain a peak triggering of say 80% of the max comparator voltage input. This gives some DAC resolution control and a bit of input protection. This 'trigger' becomes the time reference for the sampling.
Once the trigger occurs, it is shaped by the hysteresis of comp#1 and a TDR ground leg into a fixed length pulse period, suitable for use by comp#2.
The delay chip has a 2nS min, which requires the 2.5nS delay line so we can peak sample a bit BEFORE the trigger event, which I think is a useful capability.
Now once the delay chip time period is set the comp# 2 will 'sample' based on the analog Vref produced by the trigger pulse and controlled by 8 uC lines. In order to get a peak sample, the uC will have to start from a max Vref and work down via the 8 bit control until comp# 2 triggers. Using comp#2 latch setting will inform the uC of the peak detection and it can calculate the actual Vref that = peak detect based on the known amplitude of the delay trigger and the setting of the 8 DAC lines. Achieving this first peak detection will take a few cycles of the RF input while the uC steps down the DAC Vref.
Having obtained the first known Peak detection and the first known time step from the trigger based on the delay chip setting, the uC can proceed to repeat this process by resetting the latches of the comparators after adding known delays (delay chip), maxing the 2nd comparator's Vref again and resampling the signal detection (now time offset triggered from the ref. peak) thereby building up a sequential profile of the signal.
The data from the sampling can be laid off to some FRAM memory to allow for upload via USB to a PC or output via a calculated 10 bit PWM & low pass filter to a low speed scope.
Depending on the uC speed and the fact that the parallel sampled DAC Vref/ Vpeak is derived on the fly with a simple calc with no use of an ADC I'd venture that a couple hundred KSPS can be obtained.
The uC will know when a complete signal period is complete when a delayed signal sample = the peak sample. (This will require a manual tolerance tuning input by the user - perhaps by a quadrature encoder to prevent false period detection due to noise etc.). The uC can then report on frequency or perhaps do useful things like focus/zoom by oversampling of some part of the wave for better time resolution samples and improved details.
Well, time to poke some holes in the concept folks.
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