Author Topic: Schematic ERC: Conflict problem between pins, severity error  (Read 1676 times)

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Offline kandrey89

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  • Country: us
Schematic ERC: Conflict problem between pins, severity error
« on: December 22, 2016, 07:49:06 pm »
Hi,

FYI, concurrent discussion here as well: https://forum.kicad.info/t/schematic-erc-conflict-problem-between-pins-severity-error

I modularized my project so that I can make one schematic and use a single schematic for multiple audio channels.

See here, I have a single file, that's used 3 times. Each sheet name is unique otherwise problems arise, and then each component ID is unique inside the sheet. CH1 will have diff. comp.ids than CH2.

TOP is the top level schematic, bottom is the Input-Preamp CH1 schematic.



Error report:
***** Sheet /LineInput_Unbalanced_Stereo_CH1/
ErrType(5): Conflict problem between pins. Severity: error
@ (6.750 in,4.600 in): Pin 7 (Output) of component U5 is connected to
@ (6.750 in,3.200 in): pin 1 (Output) of component U5 (net 1).
ErrType(5): Conflict problem between pins. Severity: error
@ (6.750 in,4.600 in): Pin 7 (Output) of component U6 is connected to
@ (6.750 in,3.200 in): pin 1 (Output) of component U6 (net 2).
ErrType(5): Conflict problem between pins. Severity: error
@ (6.750 in,3.200 in): Pin 1 (Output) of component U1 is connected to
@ (6.750 in,4.600 in): pin 7 (Output) of component U1 (net 7).

Note that U1 is CH1, U5 is CH2, and U6 is CH3. Why it thinks all the outputs are connected together from the same schematic file doesn't make sense...

Any ideas?

Thanks
« Last Edit: December 22, 2016, 09:31:12 pm by kandrey89 »
 

Offline kandrey89

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  • Posts: 32
  • Country: us
Re: Schematic ERC: Conflict problem between pins, severity error
« Reply #1 on: December 22, 2016, 09:50:47 pm »
The SW-VOL-PAN sheet has inputs shorted out with a vertical hard to see wire!  :-DD :-// |O :palm:
 


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