It seems that net designations, such as power, to not carry through switches.
My schematic is correct and there are no ERC errors. Starting at switch “O/I-1”, pin 2, follow the net to all other connections. Now, look at the board. None of those ratwire/connections exist. Maybe it has to do with the pin output designations of the switch? How to correct, please?
A Power Flag is not the same thing as a Power Symbol.
A Power Symbol (the usual sort of VCC or whatever) declares a global net whose name is in the symbol (say VCC)
and the one pin in the symbol has an electrical type Power Input. The reason they are Power Inputs is because you'll likely instantiate more than one in a design, and if they were Power Outputs the ERC would give you a "multiple drivers on a net" error.
You should use Power Symbols for all of your power-supply rails.A Power Flag does
not give a net any label. Its pin has an electrical type Power Output. It is a trick meant to tell the ERC that, yes, there
is a driver (Power Output) on this particular net.
Why is this necessary? Consider: your battery likely has its + and - pins declared as electrical type Power Output. So you can connect them to Power Inputs and ERC is satisfied. (And you can place a Power Symbol, such as GND and VCC, on the battery terminals, which helps to clean up the schematic.) But what about instances where the power input comes from a connector, or is switched as in your case? Pin 2 of your switch is connected to a Power Input (pin 8 of U1A), so without the Power Flag ERC will say "you don't have a driver on your Power net." With the Power Flag in place, as you've done, ERC is satisfied. Assuming that your battery's negative terminal pin is declared as Power Out, the Power Flag on the GND net you've placed at U1A pin 4 is not necessary.
All that said: since your board layout doesn't have silkscreen or any other indication telling us which of the holes are the switch's pins 1, 2 and 3, it's hard to follow what is going on. That U2 is an 8-pin connector isn't helping, either -- are the pins ordered like a DIP/SOIC (increasing down one side then up the other) or are they ordered like a connector (all odd on one side, even on the other)?
Use a text editor to look at the netlist file created by EESchema and verify that the connections are actually there. And, please tell us which version of Kicad you're using. Is it 4.0.7, the latest stable? Is it a nightly build? Is it something older? What canvas are you using (OpenGL or legacy)?