Author Topic: Acceptable Yeilds from PNP line  (Read 7241 times)

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Offline jmelson

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Re: Acceptable Yeilds from PNP line
« Reply #25 on: October 05, 2018, 07:48:15 pm »
I DO have problems with high-density QFPs, though.  Some of my stencils have too big apertures, and I get solder bridges.  To fight that, I shrunk the stencil apertures, and then I have leads that did NOT solder.

Another possibility is to reduce the thickness of the solder paste stencil instead of the aperture.
I'm already down to 0.003" (~ .076 mm) to keep the apertures from just disappearing.  One thing I did find on the last run, and don't know how to fix, is that fixturing the board in a frame lead to variations in the alignment of the paste.  So, if the PCB fabricator has a lot of variation in the routing of the board exterior, I might need to realign the stencil on each board!  UGH, that would totally mess up my system, I sure hope I don't need to do THAT!

Jon
 

Offline jmelson

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Re: Acceptable Yeilds from PNP line
« Reply #26 on: October 05, 2018, 07:53:31 pm »
or if possible use QFN's.    Thats been a big bonus for me.
Well, the problem with those is you can get solder bridges UNDER the part, and there is almost no way to see them, or fix them.  I did do one board with chip-scale QFNs, and it was a NIGHTMARE.  65 chips on each board, parallel on the power rails.  Which one has the short? 

So, I'm really afraid of ever using such parts again.

Jon
 

Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #27 on: October 05, 2018, 07:56:06 pm »
A lot of people wince at QFNs and other no-leads and exposed-pads, but the truth is this: even if you don't have hot air, they're... not impossible (though to do by iron, you really need to make a big hole to access the exposed pad and glob onto that), but a passable hot air machine is cheap and gives SO, SO MUCH BETTER results, easier than using an iron.

Tim
Making a prototype with QFNs is no problem at all. Making a production quality board, with low thermal stresses, is not so trivial. Even heating takes real effort.

Im using Vapour Phase, and it made it really easy ( compartively ).   I'm not getting voiding or having to overheat it.     Where possible, going to QFN's over QFP's has really helped.
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Offline T3sl4co1l

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Re: Acceptable Yeilds from PNP line
« Reply #28 on: October 05, 2018, 07:59:46 pm »
or if possible use QFN's.    Thats been a big bonus for me.
Well, the problem with those is you can get solder bridges UNDER the part, and there is almost no way to see them, or fix them.  I did do one board with chip-scale QFNs, and it was a NIGHTMARE.  65 chips on each board, parallel on the power rails.  Which one has the short? 

So, I'm really afraid of ever using such parts again.

Jon

Shorts don't happen with correct paste application.  You have to put down a LOT of excess to get that to happen, AFAIK.

I have the luxury of most of my (commercial) designs being proto'd at a full service shop, where anything with a no-lead ends up with an "XRY" sticker on it... :P

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Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #29 on: October 05, 2018, 08:05:31 pm »
Volume definitely makes a difference.
When building small batches you are far more likely to also have parts that come in small quantities, these have often been handled or repackaged by the poorly trained monkeys that inhabit Farnells warehouses and this radically increases the likelihood of a device being presented to the nozzle that can still sneak through the optical checks (if that applies to your machine) and end up on the board. So for low volumes under ~30, I might at a squint say 90% for the SMT process is OK (ish).

However once you move onto jobs with components on nice reels or virgin trays 99+% should be the order of the day.

Tombstoning should be very rare and usually points to a footprint or layout issue. The only consistently tombstoning device I have ever encountered was an 1812 resettable fuse where the designer had out quite a lot of pad under the device. This fuse can be purchased in two variants, the one with flat ends would tombstone, the version with a channel in the end of the pad, does not. The fault however is the footprint, the fact the channel variant mitigates that is just luck.

While 99.9% would be great, if i can get to 99%, it woudl be a big improvement from my current 98%.     I'm resonably happy with the precision of the PNP line itself.  I am confident that most of my issues are related to solder paste application, and improving that part of my process will improve things.   Starting to look for a new printer. 
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Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #30 on: October 05, 2018, 08:30:06 pm »
I DO have problems with high-density QFPs, though.  Some of my stencils have too big apertures, and I get solder bridges.  To fight that, I shrunk the stencil apertures, and then I have leads that did NOT solder.

Another possibility is to reduce the thickness of the solder paste stencil instead of the aperture.
I'm already down to 0.003" (~ .076 mm) to keep the apertures from just disappearing.  One thing I did find on the last run, and don't know how to fix, is that fixturing the board in a frame lead to variations in the alignment of the paste.  So, if the PCB fabricator has a lot of variation in the routing of the board exterior, I might need to realign the stencil on each board!  UGH, that would totally mess up my system, I sure hope I don't need to do THAT!

Jon


I never assume that my boards will be consistently routed out.  Because routing tolerance is around +/- 0.15 mm or so.. ( they claim better but i'm being realistic )..   The automatic Stenciling machines have optical systems and move the boards to suit..  If your doing it manually, you have to be able to adjust each time.  It should'nt be much, but it will be a little..   


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Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #31 on: October 05, 2018, 08:31:34 pm »
or if possible use QFN's.    Thats been a big bonus for me.
Well, the problem with those is you can get solder bridges UNDER the part, and there is almost no way to see them, or fix them.  I did do one board with chip-scale QFNs, and it was a NIGHTMARE.  65 chips on each board, parallel on the power rails.  Which one has the short? 

So, I'm really afraid of ever using such parts again.

Jon

Shorts don't happen with correct paste application.  You have to put down a LOT of excess to get that to happen, AFAIK.

I have the luxury of most of my (commercial) designs being proto'd at a full service shop, where anything with a no-lead ends up with an "XRY" sticker on it... :P

Tim

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Offline SMTech

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Re: Acceptable Yeilds from PNP line
« Reply #32 on: October 05, 2018, 09:27:50 pm »
Quote
Shorts don't happen with correct paste application.  You have to put down a LOT of excess to get that to happen, AFAIK.

I actually don't think it takes all that much when you get down to 0.5mm pitch QFP and below and there are more than a couple of ways you can end up with too much paste. Apertures, stencil tension, stencil thickness,PCB/Stencil gasketing, footprint, paste age/liquidity will all play a part

Quote
I'm reasonably happy with the precision of the PNP line itself.  I am confident that most of my issues are related to solder paste application, and improving that part of my process will improve things.   Starting to look for a new printer.

One tip I would give is to ignore perhaps 90% of anything you might find on Youtube where people manually paste because it is on the whole done VERY badly. When the squeegee blade passes over the stencil the stencil should be CLEAN behind the blade, the blade should be at a fairly steep angle (30 degrees off perpendicular) so that the paste "rolls" into the apertures rather than being pushed through them by the flat of the blade, if your paste doesn't do this it is either too cold, not well mixed or f*cked.
For fine pitch boards you will want to periodically clean the underside of the stencil to make sure paste isn't affecting the PCB/Stencil gasketing but also to make sure finer apertures are not getting blocked. Fully automated machines pretty much make this a standard feature these days. If running a semi-auto setup, depending how your system works you may need to look at checking the alignment for every PCB, some rely on the board being in exactly the same place after the initial setup. Again fully automated machines align every PCB.
 
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Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #33 on: October 05, 2018, 10:03:22 pm »
One tip I would give is to ignore perhaps 90% of anything you might find on Youtube where people manually paste because it is on the whole done VERY badly. When the squeegee blade passes over the stencil the stencil should be CLEAN behind the blade, the blade should be at a fairly steep angle (30 degrees off perpendicular) so that the paste "rolls" into the apertures rather than being pushed through them by the flat of the blade, if your paste doesn't do this it is either too cold, not well mixed or f*cked.
Quote

yes, on the youtube. People using credit cards as squeegees.  the right angle is critical, and it makes a huge difference.   I cheat a bit by using GC10. the cheat is buying convience, as it every easy to mix and store.    All that said, my process is not perfect, and i'm pretty sure its contributing to the issues that i have had.

Quote
For fine pitch boards you will want to periodically clean the underside of the stencil to make sure paste isn't affecting the PCB/Stencil gasketing but also to make sure finer apertures are not getting blocked.
Quote

Yeah, this too.   

Fully automated machines pretty much make this a standard feature these days. If running a semi-auto setup, depending how your system works you may need to look at checking the alignment for every PCB, some rely on the board being in exactly the same place after the initial setup. Again fully automated machines align every PCB.
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Offline rx8pilot

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Re: Acceptable Yeilds from PNP line
« Reply #34 on: October 06, 2018, 12:18:45 am »
The majority of trouble for me has been related to solder paste. I have worked to improve my stencil designs, using better paste, electropolished stencils, and much-improved technique on the printing. Those efforts have landed me a fantastic yield on the soldering side.

As for placement.....I feel like I am always struggling with one or two parts. My latest problem is the puff-off needs a bit of TLC. Some of the capacitors are sticking to the nozzle and not coming off until the retract which drops the cap off to the side of the pads. Obviously, that is a machine specific problem and it is currently creating a problem every 1,000 placements or so. I think I should see this be in the range of every 100,000 placements.

I would be happy if I could manage 10 panels with 1,000 parts each without re-work of some kind. For a commercial assembler, that would be a marginal goal but workable for my in-house needs. If I dial in my machine a bit better....I could probably beat that target fairly well.

I inspect PCB's post printing and pre-reflow. It is much easier to fix something at those stages.
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Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #35 on: October 06, 2018, 07:02:06 am »
The majority of trouble for me has been related to solder paste. I have worked to improve my stencil designs, using better paste, electropolished stencils, and much-improved technique on the printing. Those efforts have landed me a fantastic yield on the soldering side.
Yes, also a similar story.  I'm convinced however at least for me, that spending a bit more time ( and money ) on this area will help me even more. 

Quote
As for placement.....I feel like I am always struggling with one or two parts. My latest problem is the puff-off needs a bit of TLC. Some of the capacitors are sticking to the nozzle and not coming off until the retract which drops the cap off to the side of the pads. Obviously, that is a machine specific problem and it is currently creating a problem every 1,000 placements or so. I think I should see this be in the range of every 100,000 placements.
Pull-off?   My machine pushes the part off, ( the vacumn becomes a postive ) and blows it off..  One of the things that i've found needs lots of attention is making sure that all my placment heights are set up just right.  needs to be just dropping into the paste but not too much!   Having support pins under the board ( and the board being flat) is also important.


I would be happy if I could manage 10 panels with 1,000 parts each without re-work of some kind. For a commercial assembler, that would be a marginal goal but workable for my in-house needs. If I dial in my machine a bit better....I could probably beat that target fairly well.

I inspect PCB's post printing and pre-reflow. It is much easier to fix something at those stages.
[/quote]
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Offline mikeselectricstuff

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Re: Acceptable Yeilds from PNP line
« Reply #36 on: October 06, 2018, 01:17:14 pm »
  65 chips on each board, parallel on the power rails.  Which one has the short? 
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Offline ar__systems

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Re: Acceptable Yeilds from PNP line
« Reply #37 on: October 06, 2018, 02:49:37 pm »

One thing I did find on the last run, and don't know how to fix, is that fixturing the board in a frame lead to variations in the alignment of the paste.  So, if the PCB fabricator has a lot of variation in the routing of the board exterior, I might need to realign the stencil on each board!  UGH, that would totally mess up my system, I sure hope I don't need to do THAT!

Jon
Mount the board by the holes on the PCB. Holes are drilled with a better tolerance than the router.
 

Offline coppice

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Re: Acceptable Yeilds from PNP line
« Reply #38 on: October 06, 2018, 03:26:29 pm »

One thing I did find on the last run, and don't know how to fix, is that fixturing the board in a frame lead to variations in the alignment of the paste.  So, if the PCB fabricator has a lot of variation in the routing of the board exterior, I might need to realign the stencil on each board!  UGH, that would totally mess up my system, I sure hope I don't need to do THAT!

Jon
Mount the board by the holes on the PCB. Holes are drilled with a better tolerance than the router.
Most boards have been broken out of a larger panel. The broken edges are rough, which can be the main source of vagueness in locating the board in downstream tools, like PnP. If you locate the board by a cleanly routed surface it should be better. The precision of both routed slot width or drilled hole size is not that great, though. The best location is normally against the centre location of a hole. A slightly conical locating peg of some kind, pushed into a round hole, works well.
 

Offline rx8pilot

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Re: Acceptable Yeilds from PNP line
« Reply #39 on: October 07, 2018, 02:09:21 am »
Quote
As for placement.....I feel like I am always struggling with one or two parts. My latest problem is the puff-off needs a bit of TLC. Some of the capacitors are sticking to the nozzle and not coming off until the retract which drops the cap off to the side of the pads. Obviously, that is a machine specific problem and it is currently creating a problem every 1,000 placements or so. I think I should see this be in the range of every 100,000 placements.
Pull-off?   My machine pushes the part off, ( the vacumn becomes a postive ) and blows it off.. 

P-U-F-F O-F-F
It does the same as your machine....a tiny puff of compressed air quickly releases the vacuum. I just need to clean the filter and adjust the pressure a tiny bit to get it right.
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Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #40 on: October 07, 2018, 02:48:02 am »
Quote
As for placement.....I feel like I am always struggling with one or two parts. My latest problem is the puff-off needs a bit of TLC. Some of the capacitors are sticking to the nozzle and not coming off until the retract which drops the cap off to the side of the pads. Obviously, that is a machine specific problem and it is currently creating a problem every 1,000 placements or so. I think I should see this be in the range of every 100,000 placements.
Pull-off?   My machine pushes the part off, ( the vacumn becomes a postive ) and blows it off.. 

P-U-F-F O-F-F
It does the same as your machine....a tiny puff of compressed air quickly releases the vacuum. I just need to clean the filter and adjust the pressure a tiny bit to get it right.

 :) :) :) :) :)

I bought a guage that is central zero, and it displays +/- pressures.   Was a really good thing to own.  Foruatnly on the yamahas you can manually ( via the UI ) trigger these functions individually. ). It means you can meaure it.  Gettig them all consistent really helped.
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Offline jmelson

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Re: Acceptable Yeilds from PNP line
« Reply #41 on: October 07, 2018, 02:51:14 am »
Mount the board by the holes on the PCB. Holes are drilled with a better tolerance than the router.
Yes, this is the obvious next step.  My current setup would not make that easy at all.  So, I will have to make some kind of gizmo to do this.  Something where I can mount the posts in a slotted piece that then gets mounted under the board.  I'll have to work on this.

Thanks,

Jon
 

Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #42 on: October 07, 2018, 03:11:18 am »
Mount the board by the holes on the PCB. Holes are drilled with a better tolerance than the router.
Yes, this is the obvious next step.  My current setup would not make that easy at all.  So, I will have to make some kind of gizmo to do this.  Something where I can mount the posts in a slotted piece that then gets mounted under the board.  I'll have to work on this.

Thanks,

Jon

What is your current system?  I've  been using a 2mm cut out in the corner of my panels, with quite a lot of sucess. I have some mounts that have 'pins' that are 4mm in diameter, that match them.  Its not *perfect* i do sometimes have to make minor adjustmetns for each print.   I thought that was just normal.   I include a 4mm octogon shape on the tool strip which is 100% the size of a copper ( also octogon ). and use those for the line up.    Its a 'manual' fiducial i guess.    The reason for the 100% apature there is that you want to be able to see the edge, or its possible to be slightly offset.

 
« Last Edit: October 07, 2018, 03:15:19 am by mrpackethead »
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Offline T3sl4co1l

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Re: Acceptable Yeilds from PNP line
« Reply #43 on: October 07, 2018, 03:16:19 am »
I bought a guage that is central zero, and it displays +/- pressures.   Was a really good thing to own.  Foruatnly on the yamahas you can manually ( via the UI ) trigger these functions individually. ). It means you can meaure it.  Gettig them all consistent really helped.

Gauge is helpful but may be slow, I wonder if you might have better results with a digital gauge where you can log the pressure on a scope/DAQ.  AFAIK, still not perfectly fast, but can be a good deal faster at least.

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Offline rx8pilot

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Re: Acceptable Yeilds from PNP line
« Reply #44 on: October 07, 2018, 04:19:06 am »
I bought a guage that is central zero, and it displays +/- pressures.   Was a really good thing to own.  Foruatnly on the yamahas you can manually ( via the UI ) trigger these functions individually. ). It means you can meaure it.  Gettig them all consistent really helped.

Gauge is helpful but may be slow, I wonder if you might have better results with a digital gauge where you can log the pressure on a scope/DAQ.  AFAIK, still not perfectly fast, but can be a good deal faster at least.

Tim

I have never looked at how fast the electronic gauges are. It would be a nice way to optimize the release timing. My machine is rather slow by modern standards, but the vacuum/release is still rather quick. It only takes a tiny shift in the timing to make a mess. The valve and the air pressure combined with the motion control signal all need to be friends. If I have a clogged line or a valve problem....it will take quite an effort to get to them. Fingers crossed it is only the easy stuff.
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Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #45 on: October 07, 2018, 04:23:07 am »
I bought a guage that is central zero, and it displays +/- pressures.   Was a really good thing to own.  Foruatnly on the yamahas you can manually ( via the UI ) trigger these functions individually. ). It means you can meaure it.  Gettig them all consistent really helped.

Gauge is helpful but may be slow, I wonder if you might have better results with a digital gauge where you can log the pressure on a scope/DAQ.  AFAIK, still not perfectly fast, but can be a good deal faster at least.

Tim

I guess if you wanted to check the timing out, and see how it ramps up/down it might be good.   I've just been using it for so called 'static' measuremnets.. ( turn vacumn on for nozzle, measure, turn it off.    Turn on blow air, etc etc.        I make a weekly check of it now, as its a good indicator of a problem.
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Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #46 on: October 07, 2018, 08:45:21 pm »
Spent a good amount of time yesterday looking at the issues that I have seen. ( i've been pretty good at recording them ), and what i can do to improve them and what the likely cost will be.   A freind of mine said;

"That is the age old problem in manufacturing. Based on 20+ years in the manufacturing automation space, there is a pretty simple rule. Add up your monthly trash, and see what it is costing you. Consider your rework as well. You would not believe how many companies spend more time / money trying to fix a low cost product with high cost labor. In reality 98% first pass yield is not bad for a small operation in simple terms, but the time and labor of finding and possibly fixing the 2% is the costly part. "

I've done that and come up with a number of what its costing me. It may not been perfectly accurate, but its given me a budget to work with.    The budget is big enough to spend some money on better solder paste application, which is the root cause of the majority of my problems.   

I had thought that i might be able to compare ourselves to some sort of 'industry' standard, but actually, it does'tn matter.   What matters is what we are doing!



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Offline jmelson

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Re: Acceptable Yeilds from PNP line
« Reply #47 on: October 08, 2018, 07:21:14 pm »
What is your current system?  I've  been using a 2mm cut out in the corner of my panels, with quite a lot of sucess. I have some mounts that have 'pins' that are 4mm in diameter, that match them.  Its not *perfect* i do sometimes have to make minor adjustmetns for each print.   I thought that was just normal.   I include a 4mm octogon shape on the tool strip which is 100% the size of a copper ( also octogon ). and use those for the line up.    Its a 'manual' fiducial i guess.    The reason for the 100% apature there is that you want to be able to see the edge, or its possible to be slightly offset.
OK, what I am doing now is I have a plate with a grid of 10-32 holes on 1" spacing.  (Sorry for imperial measurements, but that is what I use.)
I have adjustable bars that have a 0.062" step on one edge, so they hold the edge of the PCB, and can be tightened down to the plate.
Then, I take the frameless stencil and align it to the PCB, and tape it down with masking tape.  The masking tape forms the hinge for the stencil.
I think a major cause of the rework issues I'm now having is due to imprecise paste alignment.  So, I may have to make up something a lot more sophisticated for stencil alignment.  So, maybe a method to put the stencil in an adjustable frame, and then adjust the alignment before printing.  I was hoping to avoid that.  And, for the low-density stuff with 0805 passives and SOIC, that all works fine.  But, when I have SSOP and 0.5mm FPGAs, it just isn't good enough.

Thanks,

Jon
« Last Edit: October 08, 2018, 07:24:13 pm by jmelson »
 

Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #48 on: October 08, 2018, 07:36:48 pm »
OK, what I am doing now is I have a plate with a grid of 10-32 holes on 1" spacing.  (Sorry for imperial measurements, but that is what I use.)
I have adjustable bars that have a 0.062" step on one edge, so they hold the edge of the PCB, and can be tightened down to the plate.
Then, I take the frameless stencil and align it to the PCB, and tape it down with masking tape.  The masking tape forms the hinge for the stencil.
I think a major cause of the rework issues I'm now having is due to imprecise paste alignment.  So, I may have to make up something a lot more sophisticated for stencil alignment.  So, maybe a method to put the stencil in an adjustable frame, and then adjust the alignment before printing.  I was hoping to avoid that.  And, for the low-density stuff with 0805 passives and SOIC, that all works fine.  But, when I have SSOP and 0.5mm FPGAs, it just isn't good enough.

If your stencil is not under tension, you'll have problems, particularly as you get done in finer pitch.   There are any number of articles about this topic, just have a little google. 

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Offline mrpacketheadTopic starter

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Re: Acceptable Yeilds from PNP line
« Reply #49 on: October 08, 2018, 10:05:58 pm »
I'm thinking that buying a big solid printer that is semi-automatic will be a good thing.   This has a print area of 500 x 350, weighs 300kg,   requires air to drive it.   Cost aroudn USD$2500 ex China. Sure its not a DEK, but its also 1/10th of the cost.    Trying to get some more info on this




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