Acceptable Yeilds from PNP line

[mrpackethead]

I'm curious, to know what others consider to be acceptable yields from PNP lines.

In an ideal world, when the board comes out of the oven, everything shoudl be perfect.  the Reality seems to be a little different from that.    What rate of faults is acceptable.

[DerekG]

What rate of faults is acceptable.

Failure of 1 board in 1000. If you are getting more than this, redesign your board, modify your solder paste stencil or refine your component placements & your oven settings.

[coppice]

That depends enormously on the size/complexity of the board, whether it has awkward shaped parts on it (i.e. ones with a significant placement error rate), and on the defect rate of the components being used. Medium sized boards loaded with 6 sigma components should have >99% first pass success rate. Small boards >99.9%.

[mrpackethead]

Is there some kind of standard on this?   Too reasons;

Clearly getting it perfect is just not going to be possible, over a big enough sample.   Somethign will go wrong, sometime. 

There likely is a economically 'sweet' spot.    where the cost of process improvement will exceed the cost of faults.     At that point it makes no sense to spend more  money to make it better.  This sweet spot is likely to differ for different people.

I would love a finished board rate of 99.9% rate, but to be honest, I'm not achieving that.  I'm an order of magnitude lower than that, and probably have around 2% of boards that have a flaw.    tombstoned passives being the primary concern.   Unfortuanly some issues wont' show themselves up in testing.   for example a bypass cap, may not stop testing from working.

[mrpackethead]

http://www.rayprasad.com/three-steps-to-improve-smt-yield

This is an interesting article, and it suggests that less than 10% of companys have a FPY ( First Pass yeild ) rate of greater than 90%.   In this picture my ~98% FPY is not too bad.     @cOPPICE, what did you base your 99.9% on.

[mrpackethead]

And another article.  This one suggests a DPMO  ( Defects per Million Opportunitys ) of 500 for SMT.     I was doing a reletively low tech board that had 1388 DO's. ( joints )   

588 joints x 500Dpmo =  0.694% chance i'll have a failure on a board..       Guess if you are up in the 2-10DMPO range you migth get your 99.9%

The flip side of this is if you were buidlnig cellphones or TV's, or motherboards, where you are building Millions of units, then the engineering time required to dial in your process, is probably worth it.    For short runs, it may cost more to do that, than the cost of some rework.

My head hurts.
 

http://www.circuitnet.com/experts/87593.html

As a general rule of thumb, there is a 10X jump in defect creation between each assembly process.

SMT Reflow will, on average, have a 50 DPMO level. Wave will, on average, have a 500 DPMO level. Hand or Rework will, on average, have a 5000 DPMO level.

Even when you go to best in class, the 10X rule still tends to apply SMT Reflow best in class can be 2 to 10 DPMO. Wave best in class can be  20 to 100 DPMO.  Best in class will avoid rework at all costs
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[coppice]

http://www.rayprasad.com/three-steps-to-improve-smt-yield

This is an interesting article, and it suggests that less than 10% of companys have a FPY ( First Pass yeild ) rate of greater than 90%.   In this picture my ~98% FPY is not too bad.     @cOPPICE, what did you base your 99.9% on.

People who are best in class at first pass success rates aren't a little better than the average. They are a LOT better. A lot of it comes down to attitude. Some people shrug their shoulders and think they are probably doing the best they can. Others get competitive, and are determined to polish out every little source of failure they can. Several rounds of little bits of polishing really adds up.

Small things can substantially impact defect rates. E.G. how QFPs are handled really matters. Many people like to pre-programme MCUs before they go to the assembly shop, and blow the fuse. This might make people feel better about industrial security, but it can really hurt the first pass success rate. Some amount of legs get bent at eachmechanical handling step. More mechanical handling steps means more failures. If the repacking of programmed chips is not handled well it often ends up as the dominant source of first pass failures. This is an area where QFNs (and most other legless packages) are a boon.

A typical MCU based product, with an MCU, a few anciliary chips, and some passives, nicely panellised so the boards can be minimally handled and broken apart with low stress, should achieve 99.9% first pass success at the board level (perhaps less at the panel level, if the panel is large). People who take first pass seriously get 99.9% success on much more complex boards. If you can't get 99.9% on simple boards, how would you ever get a large complex board, like a computer server motherboard, to work at all?

[mrpackethead]

if the claim that only 10% are getting better than 90% FPY is correctly, then getting 99.9% is amazing.    its 100x better.   I know that I'm getting better rates than my old contract manufactuers did.   Maybe becuase i actually care about my work, maybe because i am doing a better job of optimizing my designs for our line.
Maybe because for the main, i can get solder paste on the boards relaibly!

I'd like to get higher than 98%.         But Polishing costs money.  I'm often doing projects in teh order of 100-500 units.    Two approaches..  If i was making 500,id expect 10 to have an issue.    I could just overmake units..  and not bother to fix the broken ones.  This sounds wasteful, but it might be the best way.   ( an increase of 2% costs of materials ).   Or i could take the hit and fix thm.    Either way, its possiby cheaper than spending a week or more time to make the required changes, to optimize things better.   On a job when your going to make 10,000,000 then it certainly makes sense.     

There are things i've done that have made great improvements.   

- I moved to using GC10 paste.  For small runs its so easy to use, its a big time saver
- I upgraded stencil printer.  That made a big improvement.
- I dont' let the Stencil manufacturer do stencil reductions... Its all calcualted.

I agree with you, the use of QFN's over QFPs' are a great thing.

I'm not in this game to get 99.9% rates. I'm in it to optimize profits.  I'm trying to figure out where teh right target should be.

[coppice]

if the claim that only 10% are getting better than 90% FPY is correctly, then getting 99.9% is amazing.    its 100x better.

A well polished line getting 100x less defects than a less well polished line is not strange at all. That's how statistical processes work.

I'd like to get higher than 98%.         But Polishing costs money.  I'm often doing projects in teh order of 100-500 units.

Much of the polish needed for high yields has little to do with your run size. Its a matter of polishing your processes, so runs of every design you produce can benefit. There will always be some design specific factors, but if you get your underlying processes right you can see big improvements across all designs. If you've never tried them, you might be surprised how far simple things like check lists can take you. Every time you have a production problem, add the cause of the problem to a check list, so its one of the things you specifically look for in future designs, before you sign them off and make a batch. Remember the circuitry changes a lot for each new board, but only a small number of production related things, like a weird new connector, change. Keep what is common as common as possible, and polish it.

[Araho]

I'd like to get higher than 98%.         But Polishing costs money.  I'm often doing projects in teh order of 100-500 units.    Two approaches..  If i was making 500,id expect 10 to have an issue.    I could just overmake units..  and not bother to fix the broken ones.  This sounds wasteful, but it might be the best way.   ( an increase of 2% costs of materials ).   Or i could take the hit and fix thm.    Either way, its possiby cheaper than spending a week or more time to make the required changes, to optimize things better.   On a job when your going to make 10,000,000 then it certainly makes sense.     

[...]

I'm not in this game to get 99.9% rates. I'm in it to optimize profits.  I'm trying to figure out where teh right target should be.

You will generally always have a larger number of passives available anyway, and you'd probably buy some stock of others for rework/repair etc. If so, making a few boards more than the customer ordered while running the process anyway makes sense. Not necessarily completing the product with enclosures etc for all of them, just minimizing the time-to-customer in case of production defects and for RMA's.

If you are producing to stock and not to order (which sounds more likely with ~500 boards), this is not as big of a deal in my opinion.

Although to me who's fresh in the game, 98% first-pass with no rework sounds damn good! 

[coppice]

Although to me who's fresh in the game, 98% first-pass with no rework sounds damn good! 

Superficially it seems like if you get 98% first pass success you can simply throw away the 2% that fail, and your costs are not horrible. The snag is that if you only get 98% to pass first time, you probably have some percentage of marginal passes that will fail in the field. When you get 99.9% first pass success your processes are usually tight enough to massively reduce the marginal passes as well as the hard failures, and reliability is much better.

[Araho]

Excellent point about reliability! (Just to be clear, I meant first-pass as in first built revision of design - which still seems a bit daunting. Although that probably counts as design issues, not production fault I guess)

[DerekG]

I could just overmake units..  and not bother to fix the broken ones.  This sounds wasteful, but it might be the best way.   ( an increase of 2% costs of materials ).

It is always best to examine at least some of the failed boards as you often find that the failures are due to the same assembly fault. It might simply be a solder bridge or open circuit at the same spot on the board (which is quick to fix once it has been located the first time).

[ar__systems]

If so, making a few boards more than the customer ordered while running the process anyway makes sense. Not necessarily completing the product with enclosures etc for all of them, just minimizing the time-to-customer in case of production defects and for RMA's.

That's how proper manufacturers operate. If I order 1000 of something, the quote will stipulate they are allowed to overship, up to 1020 or so.

[T3sl4co1l]

I'm not in this game to get 99.9% rates. I'm in it to optimize profits.  I'm trying to figure out where teh right target should be.

This isn't a question of PNP performance and oven profiles.

Not yet.

This is a question for your spreadsheets. What is the cost breakdown for hand rework?  How does the added build time affect your customers (are they willing to pay more for faster guaranteed builds, or are you stuck with competitive pricing)?

Then you can ask about how much effort it will take to improve your process.  This includes footprints (which probably come from the customer, in which case you'll need a DFM process to verify their designs are likely to have good results with your house process), solder paste (which may or may not come from the customer -- I've never been asked to make paste changes myself, and assume the assembly house takes care of it), and programming and fine tuning of the various machines involved (are your PNP machines calibrated correctly? is your oven set to the right profile for the size and kind of board, number of components, type of paste, etc.?).

(Or maybe you've already done the first analysis, and that's why you're asking the step ahead.)

Tim

[mrpackethead]

This isn't a question of PNP performance and oven profiles.

No, its about questions of everything we do.

This is a question for your spreadsheets. What is the cost breakdown for hand rework?  How does the added build time affect your customers (are they willing to pay more for faster guaranteed builds, or are you stuck with competitive pricing)?

For me, we are *only* doing PNP for products we design and are selling as completed items.  We are not contract manufacturing.       Added build time in most is'nt the end of the world,  however, it does cost.     Rework costs $65/hour, in real costs.    ( staff costs + plant + overhead ).   Its something to avoid as far as we can.   That being said we are not making commodity electronics. ( yet ).


Really the question, ( just to clarify it ) was about finding a yard stick to compare ourselves against.     Coppice suggested that 99.9% would be a rate.    that would be an improvement of about 20x over what we are currently achieving.   ( I will add right now that we are doing a better job than our old CM did, and each job we do, we seem to get better ).    The differnece being that in a small company we dont' have dedicated people doing every task.

[mikeselectricstuff]

One product I'm really glad I don't have to make is the LED tiles for video walls - the higher density ones have 4096 LEDs with almost no space between them, which must be near-impossible to rework, so off-the-machine yield has to be very high for them to be under $50 1-off shipped :

e.g. This one

Though I suppose the high volume and specialisation mean they may have custom jigs for reworking them.

Back on-topic there's always going to be a tradeoff between time spent optimising the process and rework or scrap costs. For lower volumes, it may well be cheaper to only look at the low-hanging fruit when optimising.

[jmelson]

Is there some kind of standard on this?   Too reasons;

Clearly getting it perfect is just not going to be possible, over a big enough sample.   Somethign will go wrong, sometime. 

There likely is a economically 'sweet' spot.    where the cost of process improvement will exceed the cost of faults.     At that point it makes no sense to spend more  money to make it better.  This sweet spot is likely to differ for different people.

I would love a finished board rate of 99.9% rate, but to be honest, I'm not achieving that.  I'm an order of magnitude lower than that, and probably have around 2% of boards that have a flaw.    tombstoned passives being the primary concern.   Unfortuanly some issues wont' show themselves up in testing.   for example a bypass cap, may not stop testing from working.

Interesting!  I have such a rare occurrence of true tombstone parts it is surprising.  I do occasionally see a resistor that is only soldered on one end.  But, in thousands of boards, I have only seen, maybe 5 tombstones with the part flipped vertical.  This may have something to do with the thermal control of the oven.  I use a GE toaster oven with 4 rod-type IR elements, and a thermocouple ramp-and-soak controller with a thermocouple poked into a PTH on one of the boards.

I DO have problems with high-density QFPs, though.  Some of my stencils have too big apertures, and I get solder bridges.  To fight that, I shrunk the stencil apertures, and then I have leads that did NOT solder.  I haven't really found a sweet spot, yet.  I just changed over to Loctite GC10, but haven't done enough boards with it to know how much it helps.  I'm using a lot of Xilinx parts in the 144-pin 0.5mm pitch QFP package, and those are the ones giving me fits.  0805, 0603 and SOIC parts are pretty close to 100% perfect.

Jon

[mrpackethead]

.
Back on-topic there's always going to be a tradeoff between time spent optimising the process and rework or scrap costs. For lower volumes, it may well be cheaper to only look at the low-hanging fruit when optimising.

Yes. exactly.

[DerekG]

I DO have problems with high-density QFPs, though.  Some of my stencils have too big apertures, and I get solder bridges.  To fight that, I shrunk the stencil apertures, and then I have leads that did NOT solder.

Another possibility is to reduce the thickness of the solder paste stencil instead of the aperture.

[mrpackethead]

I DO have problems with high-density QFPs, though.  Some of my stencils have too big apertures, and I get solder bridges.  To fight that, I shrunk the stencil apertures, and then I have leads that did NOT solder.

Another possibility is to reduce the thickness of the solder paste stencil instead of the aperture.

or if possible use QFN's.    Thats been a big bonus for me.

[mikeselectricstuff]

An issue with low volume production is you may not get enough failures to identify specific causes above the noise of random occurrences, or measure the effect of changes to the process to a statistically significant level.

[T3sl4co1l]

A lot of people wince at QFNs and other no-leads and exposed-pads, but the truth is this: even if you don't have hot air, they're... not impossible (though to do by iron, you really need to make a big hole to access the exposed pad and glob onto that), but a passable hot air machine is cheap and gives SO, SO MUCH BETTER results, easier than using an iron.

Tim

[coppice]

A lot of people wince at QFNs and other no-leads and exposed-pads, but the truth is this: even if you don't have hot air, they're... not impossible (though to do by iron, you really need to make a big hole to access the exposed pad and glob onto that), but a passable hot air machine is cheap and gives SO, SO MUCH BETTER results, easier than using an iron.

Tim

Making a prototype with QFNs is no problem at all. Making a production quality board, with low thermal stresses, is not so trivial. Even heating takes real effort.

[SMTech]

Volume definitely makes a difference.
When building small batches you are far more likely to also have parts that come in small quantities, these have often been handled or repackaged by the poorly trained monkeys that inhabit Farnells warehouses and this radically increases the likelihood of a device being presented to the nozzle that can still sneak through the optical checks (if that applies to your machine) and end up on the board. So for low volumes under ~30, I might at a squint say 90% for the SMT process is OK (ish).

However once you move onto jobs with components on nice reels or virgin trays 99+% should be the order of the day.

Tombstoning should be very rare and usually points to a footprint or layout issue. The only consistently tombstoning device I have ever encountered was an 1812 resettable fuse where the designer had out quite a lot of pad under the device. This fuse can be purchased in two variants, the one with flat ends would tombstone, the version with a channel in the end of the pad, does not. The fault however is the footprint, the fact the channel variant mitigates that is just luck.