cheap 3/3 mil, 4 layer, PCB prototype manufacturer?

[FrankBuss]

I'm planning a board with a FPGA, BGA with 0.4 mm pitch, 64 balls, which probably needs 3 mil traces and 3 mil spacing. I found https://www.pcbcart.com , where I can select 0.07 mm, if I select 4 layers for the Standard PCB quote calculator, which might work, and I need 4 layers anyway for a clean supply and GND plane. But for 10 PCBs, 5 cm^2, it would cost $288 (it is quiet cheap for larger quantities). Is there a cheaper prototype service? Looks like the technical term for this is HDI PCB, but many companies don't publish their prices, but you have to send a PCB for quote, which I will do, but maybe someone knows already a cheaper good service.

[wraper]

Try wellpcb, it should be much cheaper. PCBcart is expensive, especially at low quantities.

[FrankBuss]

Thanks, this looks very good. 10 PCBs, 5 cm^2, 4 layers costs $41, and they write that they can do 3 mil / 3 mil, that's very affordable. I hope the quote is valid for the 3/3 process as well, but will try it.

[NorthGuy]

Thanks, this looks very good. 10 PCBs, 5 cm^2, 4 layers costs $41, and they write that they can do 3 mil / 3 mil, that's very affordable. I hope the quote is valid for the 3/3 process as well, but will try it.

There's a red "Full SPECS" button on the bottom. You can click it and select 3mil. Even if you do that and also select ENIG, it still comes at $88 which is an excellent price.

[asmi]

For 0.4 mm pitch BGA you will need via-in-a-pad process - it will make your life much easier. Basically after plating vias, they are going to plug them with resin or something like that, and after that will add some more plating on top.
You can email Candice from OurPCB at sales01@ourpcb.com as well - they seem to be the same as WellPCB, but this is the person I've personally done business with, so I can tell he's good and responds pretty quickly. Just send him the specs and see what he says. For controlled impedance, they will tell you to design stackup yourself, which is a big advantage IMHO as you can choose the one so that high-speed traces will have sensible width. I didn't ask about via-in-a-pad, but when I asked for 10 4 layer 10x10 cm boards 1.2 mm thickness, 0.1/0.1 mm traces, 0.2 mm drills, lead-free HAL and controlled impedance, he quoted me $142.27 (that price includes DHL express shipping to Canada).
UPDATE: But now as I thought about this, you will need laser-drilled 0.1 mm microvias to break out that kind of BGA, as 0.2 mm drills will not fit between balls. This is going to be expensive.

[FrankBuss]

I plan to use a 64-ball ucBGA FPGA, see page 6 here:

http://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/PT/PCBLayoutRecommendationsforBGAPackages.pdf

Looks like they didn't use via-in-pad. wellpcb can do 0.15 mm drills. Would this be too big?

I just tried it in KiCad:



There are 2 pads, 6 mil diameter, and a via, 10 mil diameter and 6 mil drill (which would be 0.1525 mm). The distance between the edges of the via and the pads are about 3.1 mil.

[asmi]

There are 2 pads, 6 mil diameter, and a via, 10 mil diameter and 6 mil drill (which would be 0.1525 mm). The distance between the edges of the via and the pads are about 3.1 mil.

10 mils is about 0.25 mm, so you will have only 0.15 mm between vias - that's not enough to fit a trace between them as you need at very least 9 mil ~ 0.225 mm (3 mils for the trace and 3+3 mils for spacings around it). Also note that example you mentioned uses blind vias with very small pads (take a look at layer 3 pads compared to traces - these pads are barely twice the width of the trace!).

[FrankBuss]

Right, I didn't think this to the end. So looks like it has to be either via-in-pad or microvias. With laser drilling, I would have to pay like $500 at PCBcart.

[asmi]

Right, I didn't think this to the end. So looks like it has to be either via-in-pad or microvias. With laser drilling, I would have to pay like $500 at PCBcart.

Unless you absolutely need to use IC in this package, I'd recommend you to pick larger package. I suspect it's going to be cheaper in the end, even if that larger package will be slightly more expensive.

[FrankBuss]

My idea was to build a universal programmable TTL IC replacement board, for all packages from DIP 14 to DIP 20, and with individual voltage level translators for individual pin directions for each pin (but not for the special TTL ICs, like high voltage open collector, only 3.3V/5V digital functions). With pin headers at the side, I can't use much bigger ICs. And SMD pin headers don't look very durable, if you plug them often in a breadboard.

But maybe I could do a 2 level construction. Then I could use ICs up to 1 cm width. Might be cheaper in the end, then one HDI PCB.

[NorthGuy]

With pin headers at the side, I can't use much bigger ICs. And SMD pin headers don't look very durable, if you plug them often in a breadboard.

You can mount your board vertically with 2 rows of 90-degree bent pins - one row on one side and the other one on the other side. Then you have as much space as you want. They sell pins of different length, so you can do such arrangement with TH pins - longer pins on one side and shorter pins on the other.

Another idea is to use horizontal PCB, but instead of mounting ICs on it, you can mount only a header in the middle (similar to PCIe header). Then you can insert boards with ICs into the header and switch them without taking the main PCB out of the breadboard.

[FrankBuss]

In the iPhone teardown, at step 13 here, you can see a nice method with a spacer PCB. I think this would allow a very low profile, but might be challenging to solder it. Vertically mounted, or horizontally with some sort of connector, might not fit sometimes, if there is not much room above (thinking of e.g. repairing retro computers).

[asmi]

Ok, I got curious enough to actually try breaking it out. I used 0.15 mm drill/0.225 mm pad vias and 0.075 mm traces. This way I was able to break out two outer rows on the top layer (Lattice recommends 0.17 mm pad size, so you will have just enough spacing to fit a trace between balls), third row can easily be broken out on another signal layer. Forth row (4 pads) are GND/VCC pads (I used LC4064ZE part in ucBGA-64 package) and so they can connect to power and ground layers respectively.

Sorry for confusing you. I'm just so used to breaking out massive BGAs so that whenever I think about BGA breakout, I immediately think about how many traces will I be able to fit between vias. But in this case there is no need to fit any traces between vias

BTW, there is another trick that can be useful in tight situations - you can remove via annual ring on layers where they don't need to connect to anything. This way you will gain more space to fit a trace. I'm not sure if KiCAD supports such vias though - if not, it can theoretically be done directly in Gerbers as a post-process. I'm using Orcad and it does support it (they call this feature "Dynamic unused pads suppression"). Here is a video showing how it works: