OK to have zero size via pads on outer layter of 4L PCBs?

[mikeselectricstuff]

Just looking at the feasibility of a potential stupidly dense design on a 4 layer PCB
Ideally it would use a lot of blind vias between layers 1-2 and 3-4, but it seems this is an expensive process (compared to buried vias between 2-3).

I may be able to live with all the vias going all the way though if I could avoid having via pads on the layers that the don't connect to, particularly the outer layers.
so for example I'd have a 0.15mm hole with 0.4mm pads on layers 1&2 only, or 3 & 4 only. 

This is low-volume so needs to be compatible with a normal process

I don't think I've seen a board like this, but can't immediately think why it shouldn't be possible - Anyone done this?
 

[T3sl4co1l]

Hmm, I should think it has to connect to at least one layer, else how are they going to plate the barrel?

That said, once upon a time I ordered boards with NPTH holes through standard proto -- the NPTHs came back dutifully plated, despite having no annular ring and no connecting copper.  (They were then reamed out to clear the plating.)

Do you know anything about standard micro vias or laser drilled?

Tim

[mikeselectricstuff]

Hmm, I should think it has to connect to at least one layer, else how are they going to plate the barrel?

yes they do - 1&2 or 3&4

[free_electron]

neat idea but not manufacturable.
here's why :

the core is etched first. two outer layers with solid copper are added.
now you need to drill.
perform plating
now photoresist is added. this resist is open over the barrel ( negative process )
they apply tinflash in the barrel and on the annular ring.
then resist is stripped and the resist removed.
the tinflash protects the copper against etching ( sodium persulfate only eats copper , not tin )

if you do not have an annuylar ring the edge of the plated copper would be exposed leading etchand to seep in between the wall of the barrel and the pcb material.

you need a minimum annular ring to prevent this.

due to registration errors in drilling ( typical 2 to 3 mil) they want to see a 6 mil annular ring of 6mm. so, even if you are off 3 mil there is still 3mm material covering the edge of the barrel

why don't you use via in pad ? that way they simply plug the via's in one shot and plate em shut.
no need for stacked via's.  and this process is much cheaper

after plating they screen print conductive expoy in the holes , cure it , sand it down ( planarisation) and then plate the entire board again .. expse , tinflash, strip and etch.

[mikeselectricstuff]

neat idea but not manufacturable.
here's why :

Thanks - that was the info  I was looking for!
Fortunately it shouldn't be too much harder to do as two 2-layer boards that can be stacked.

[IconicPCB]

Mikeselectric,

I make PCBs commercially using mechanical milling process.

It is not a problem for me to etch away any copper anywhere on the surface of the multilayer board.

[WarSim]

neat idea but not manufacturable.
here's why :

By your answer it suggests alternate buildups so are no longer possible. 
Every layout software title I have ever used starts with a buildup definition. 
Most will warn on buildup definition violations. 
Is this all ignored now?

I know the board was shopped out to specific manufactures depending on the design, of which buildup was a factor. 

I have never shopped out my own boards.  Most likely the main reason your answer confuses me.  Especially because I have never seen any board maker state their buildup process was fixed to only one buildup.

The reason I am so interested is I am semi-retired now so I will be shopping out my own boards now. 


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[mikeselectricstuff]

neat idea but not manufacturable.
here's why :

By your answer it suggests alternate buildups so are no longer possible. 
Every layout software title I have ever used starts with a buildup definition. 

That doesn't mean that buildup is manufacturable (at a sensible cost).
Like I said, I need to keep to standard processes.
It was only when I re-watched the Eurocircuits video that I realised that 4L is built from the core outwards, not as two 2Ls that get stuck together.
 

[WarSim]

Yes each board house has a Standard process, and deviating cost extra.  Depending on board house how much more varies.  This is one reason why we contracted out to different board houses. 

What I previously though you said was.  Some how all the various board houses decided on one specific standard.  Also that the other buildups have been all but abandoned.     

If there is one "standard" buildup, this makes little sense to me.  Then again there is no law about making sense. 


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[Rufus]

If there is one "standard" buildup, this makes little sense to me.  Then again there is no law about making sense. 

Plating holes (normally #1) requires solid copper at both ends so must be done before etching. You can only etch the outside of a board or stack component. You can bond boards together, you can bond copper on the outside, you can probably sandwich copper planes between boards.

Those requirements lead to not many ways to make build up.

#1 you can do pick drilling where you only drill deep enough to hit copper on an inner layer and plate the hole with solid copper only at one end to create a blind via.

[mikeselectricstuff]

So I just managed to do it with 0.15mm via holes and 0.125mm track/space...

[T3sl4co1l]

LED matrix?

Tim

[mikeselectricstuff]

LED matrix?

Tim

Yes - 1.5mm pitch, 0402 LEDs 32x32 matrix driven as 16x64

[AlfBaz]

So I just managed to do it with 0.15mm via holes and 0.125mm track/space...

Hi Mike.
I looked into this some time ago and I asked PCBCART if they could do it. The response was "yes, no problems, no extra cost".
Still I decided against it as I couldn't ascertain how it was manufactured and had concerns about manufacturability
Good to see that it is indeed possible

Just to clarify, are the following two pictures something along the lines of what you have done? The first pic is with a pad on every layer the second with pads on 2 and 4 only. The main feature being no pad on the outer layer

[mikeselectricstuff]

So I just managed to do it with 0.15mm via holes and 0.125mm track/space...

Hi Mike.
I looked into this some time ago and I asked PCBCART if they could do it. The response was "yes, no problems, no extra cost".
Still I decided against it as I couldn't ascertain how it was manufactured and had concerns about manufacturability
Good to see that it is indeed possible

Just to clarify, are the following two pictures something along the lines of what you have done? The first pic is with a pad on every layer the second with pads on 2 and 4 only. The main feature being no pad on the outer layer

The second pic is what I was interested in doing, to make space on outer layers where the via doesn't need to connect to that layer.

[Scrts]

I use such thing all the time without any issues. When you have to route two tracks between BGA pads and there's also a VIA for one of the pads, then it's the only way to go.

[Korken]

I have been trying to do this in Altium (removing the via pad on some layers).
How do you do this? I've tried using drill pairs, but didn't get it to work.

[free_electron]

Place via. Double Click Via.

Set 'diameters' to 'FULL STACK'

edit the annular ring for every layer.

[Korken]

Thank you! Of course I didn't look in the obvious place... 

[AlfBaz]

Place via. Double Click Via.

Set 'diameters' to 'FULL STACK'

edit the annular ring for every layer.

In multilayer designs, pads on unused layers can be considered "mini-stubs" in high speed designs. I could of sworn somewhere in the past there was an option to prevent pads on unused layers. Am I misremembering or have they gotten rid of it/buried it somewhere?

[T3sl4co1l]

Rings on non-connecting layers is an export setting.  In Outjob / Gerber output.

Tim

[AlfBaz]

Rings on non-connecting layers is an export setting.  In Outjob / Gerber output.

Ah ok, that rings a bell.
There may also have been an option like that in a script I was using to export to hyperlinx before they included it