EEVblog Electronics Community Forum
Electronics => Manufacturing & Assembly => Topic started by: asmi on November 11, 2017, 05:05:19 am
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Hi guys,
I've just posted a quick review of OurPCB fab which manufactured for me 10 6-layer boards 10x10 cm each with 0.1/0.1 mm trace/spacing, 0.2 mm drills, controlled impedance and custom stackup, and all of that for $237.33! I personally think the price is a bargain. I know that some other people here are looking for affordable manufacturer for mid-spec multi-layer boards like mine, so I decided to share it here.
The post is turned out to be quite long, so I posted it into my (almost empty) blog here: http://thingselectronic.blogspot.ca/2017/11/ourpcbcom-pcb-fabrication-house-review.html (http://thingselectronic.blogspot.ca/2017/11/ourpcbcom-pcb-fabrication-house-review.html) If you are someone like me, who would like to make that next step up in complexity of your projects, but don't want top break the bank - I definitely recommend you to take a look.
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Yeah, used them before.
OurPCB is good when you need something a bit more advanced with good quality but still at a good price.
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Bookmarked!
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OurPCB=WellPCB.
Good quality, see my post in the other thread: https://www.eevblog.com/forum/manufacture/how-to-order-10-50-my-own-pcb/25/ (https://www.eevblog.com/forum/manufacture/how-to-order-10-50-my-own-pcb/25/)
WellPCB quotes $99 for 5 100x100mm 6-layer ENIG boards. This is substantially less than $237.
BTW: All Chinese PCB manufacturers use the same quoting software which always ask if vias are tinted or not. What does it mean? The gerber file specifies whether vias are covered by soldermask or not. Worse yet, I can have some vias covered (as under BGA) and some not (as TPs for testing). Are they going to alter my design to fit my answers? If not, what is the reason to ask?
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WellPCB quotes $99 for 5 100x100mm 6-layer ENIG boards. This is substantially less than $237.
My order was for 10 boards, you also need to specify impedance control and "Track Width/Space: 3-4mils" (which you can't specify together in their quote system for some reason). This brings the quote more-or-less to what I paid for the order once you add shipping charges.
BTW: All Chinese PCB manufacturers use the same quoting software which always ask if vias are tinted or not. What does it mean? The gerber file specifies whether vias are covered by soldermask or not. Worse yet, I can have some vias covered (as under BGA) and some not (as TPs for testing). Are they going to alter my design to fit my answers? If not, what is the reason to ask?
This option is applicable if you send a project file instead of gerber files. In allpcb's quote form, there is a note to that effect: "*For Gerber files, This choose is useless. it will be made according files as default."
But it's best to send Gerbers as it's the only way which gives you full control over resulting boards.
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My order was for 10 boards, you also need to specify impedance control and "Track Width/Space: 3-4mils" (which you can't specify together in their quote system for some reason). This brings the quote more-or-less to what I paid for the order once you add shipping charges.
I missed this option. When I click "Track Width/Space: 3-4mils 10% Extra" the price doubles to over $200. This is an interesting treatment for "10% Extra". But the price is great nonetheless and the quality is excellent based on your pictures. I can live with 5mil trace anyway, so it's even better.
How did you request the custom stackup? Do you know what is their default stackup?
This option is applicable if you send a project file instead of gerber files. In allpcb's quote form, there is a note to that effect: "*For Gerber files, This choose is useless. it will be made according files as default."
But it's best to send Gerbers as it's the only way which gives you full control over resulting boards.
Thank you. This explains the puzzle. It never actually occurred to me that you can submit anything but gerbers.
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I missed this option. When I click "Track Width/Space: 3-4mils 10% Extra" the price doubles to over $200. This is an interesting treatment for "10% Extra". But the price is great nonetheless and the quality is excellent based on your pictures. I can live with 5mil trace anyway, so it's even better.
I think if would be best if you'd email them all parameters and request a quote for it. I can't get myself to trust these online quote systems in all but very simple cases. Designing a 6-layer board takes a long time, so I didn't want to begin this process until I was confident I could actually afford to manufacture it afterwards. The quote I was provided with was good for 30 days, which is plenty of time to complete design without rushing anything, and it gives you somewhat of assurance that price won't suddenly shoot into the sky.
How did you request the custom stackup? Do you know what is their default stackup?
When I've asked them about stackup, here's a response I received verbatim:
My factory said they can not provide you the stack up file now. Because you need impedance control. When you have a gerber file and told me which trace need impedance contral, the factory can adjust the stack up file to meet you request of the impedance control.
Since you need *some kind of stackup* to base your design off of, I went ahead and designed the stackup myself based on cores and prepregs that are commonly used in the industry. They did tell me that dielectric constant of FR4 they use is 4.5. Then I provided a screenshot of the stackup from Orcad PCB editor that I used to calculate traces, as well as included a text file describing stackup and specifications for CI traces (trace width, ref layer #, expected impedance, diff trace width and gap, diff trace impedance) . In case you're interested, here's the exact package I've sent them: https://1drv.ms/u/s!AkGeV4xlumxj6xk0oycLAwCPVPC3 There is "!Info.txt" file with all that information.
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Hi Asmi,
Thanks for taking the time to place this post - it's exactly what we are looking for and perfect timing. We have an 8L 4/4 0.2mm proto board that has just been completed and are looking for alternate supply sources right now.
I'll be sure to let you know how things work out.
Thanks again - Peter
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When I've asked them about stackup, here's a response I received verbatim:
My factory said they can not provide you the stack up file now. Because you need impedance control. When you have a gerber file and told me which trace need impedance contral, the factory can adjust the stack up file to meet you request of the impedance control.
Looks like what they're trying to say that if you don't request "Impedance Control", you can get any stackup they want. If so, to get anything in particular you need to request "Impedance Control". Anyway, the price they have for their boards, given that you get the stackup you want is great.
@blueskull: How do you know WellPCB is the same as OurPCB? They look different to me. And the quality of OurPCB's boards on asmi's pictures appear to be better (to my eyes anyway) than the WellPCB's boards you have posted.
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Looks like what they're trying to say that if you don't request "Impedance Control", you can get any stackup they want. If so, to get anything in particular you need to request "Impedance Control". Anyway, the price they have for their boards, given that you get the stackup you want is great.
To be honest I have a hard time imagining 6+ layer board project which doesn't have any high-speed traces. So to me this seems more like an academic discussion.
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Thanks for bringing this one up. This fills a bit of a hole for me, so i'm goign to give them a shot.
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Mine doesn't look that nice is because it uses 4 mil process and a lot of non-IPC standard, extremely small pads (for instance, my 0402 footprint is 0.6mm*1.0mm). My design is approaching their limit.
Also, via-in-pad without plugged vias look inherently nasty, but it works.
This is a strange board indeed. Does the board impersonate a QFN chip?
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Mine doesn't look that nice is because it uses 4 mil process and a lot of non-IPC standard, extremely small pads (for instance, my 0402 footprint is 0.6mm*1.0mm). My design is approaching their limit.
Also, via-in-pad without plugged vias look inherently nasty, but it works.
Mine uses 0.1 mm process. As per QA certificate, the smallest trace is 4.1 mil, and smallest spacing is 3.7 mil. The board also contains few dozens of 0201 caps, its' pad size is 0.3x0.35 mm IIRC.
After thorough inspection under x20 stereo microscope, the only thing I could find was ever so slightly offset soldermask (less than 0.025 mm offset) - I could only see the offset under microscope. Everything else was perfect!
These boards are the best I've ever seen - even very small silkscreen letters (0.64 mm height) is quite readable. Comparing them to regular "$5 boards" is just silly.
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Can you post a copy of your report? I would like to see if the company name matches.
I will post it in the evening as I don't have them with me at work. Can you please post yours? Just want to compare reports as I noticed one thing odd in my report - my report says boards are thicker than they actually are according to my measurements.
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I can live with 5mil trace anyway, so it's even better.
BTW, I missed 5 mil part. Keep in mind that with 5 mil traces you can not do this:
(https://i.imgur.com/m0Mi3d3.png)
You need 4 mil/0.1 mm traces for that, and I think this alone is a reason enough to go for 0.1 mm traces.
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I can live with 5mil trace anyway, so it's even better.
BTW, I missed 5 mil part. Keep in mind that with 5 mil traces you can not do this:
(https://i.imgur.com/m0Mi3d3.png)
You need 4 mil/0.1 mm traces for that, and I think this alone is a reason enough to go for 0.1 mm traces.
That is true. But often you can work out something. For example, look at the dogbone just south of the area you marked in red. If you turn it right 45 degrees (so that it becomes horizonral), it'll give the room for the trace to escape. You could use this space to split the two side-by-side traces giving each of them its own spot. You could do similar thing to the dogbone on the top, or you could put a trace into the slot left of the dogbone.
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That is true. But often you can work out something. For example, look at the dogbone just south of the area you marked in red. If you turn it right 45 degrees (so that it becomes horizonral), it'll give the room for the trace to escape. You could use this space to split the two side-by-side traces giving each of them its own spot. You could do similar thing to the dogbone on the top, or you could put a trace into the slot left of the dogbone.
This will likely screw up escapes for internal layers, as they go between dogbone vias right under BGA balls. Having ability to route two traces between balls/vias gives a lot of flexibility and help to reduce amount of layers needed for full breakout. This is especially important for DDR3 DQ byte groups as all traces within a group needs to be routes on the same layer to minimise DQ-to-DQ skew. If you take a look at my gerbers, you will see that I route two DQ byte groups on adjacent layers, and each group is routed on the same layer. For ADDR/CTRL lines this is not that critical, but still I tried to account for that by making traces on layer 3 slightly longer than on layer 4 (as z-height of layer 3 is less than that of layer 4).
You can fully route out 6 outer rows in just two layers - first 3 on top layer, and other 3 on the next internal one (since there will be on breakout vias for outer 3 rows as you break them out directly on the top layer), where with just one track between balls/vias you will need 4 signal layers to achieve that (2 rows on the top, 2 more on the first internal, the rest will allow only one row per layer due to presence of dogbone vias from previous layers - unless you go for blind vias). So 2 layers saved right here!
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Thanks for taking the time to take all the photos and write it up!
This will likely screw up escapes for internal layers, as they go between dogbone vias right under BGA balls. Having ability to route two traces between balls/vias gives a lot of flexibility and help to reduce amount of layers needed for full breakout.
It's also a big help with the MGTs and Diff pairs. I've got 32 sublvds pairs to break out on the Artix (484 pin). And since bank 14 is needed for configuration, I can't use it for HiSPI, leaving 15 and 16.
It's a tough job getting that many pairs out, with 5 mil trace. I've routed myself into a corner more times than I can count at this point. (Note I'm referring the the FG package, the FB requires smaller pads)
In some cases a second row pair has to split either side of a VSS ball and via. With 4mil one pair fits either side of the ball.
(I don't have m laptop with me today or I'd post a couple screen grabs of the design rule comparison I've been doing to see what direction to go.)
Also package size is a big factor, on a 256 or even 484 on 6 layers, and mostly lower speed signals you can get by with 5mil traces and get a decent fanout.
On the 900 pin package, unless you have layers or pins to burn, 5mil isn't going to be fun.
I agree with NorthGuy, in quite a few cases you can route around it and when it costs $400 - $1k a pop I do.
At $200 ish, my time and sanity is well worth the premium.
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The real test is to see if you can still get good quality after the fourth or fifth order.
In my experience nearly every chinese fab starts to screw you around that time, you have to go elsewhere for a while.
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You may be right. I can get 1-board 6-layer 5 mil order from PCB-Pool for about $130, which is $650 if I go through 5 iterations until it works as I wish. When I looked at different quotes for 4mil couple months ago, it was around $600 for 4mil process, which means $3k for 5 iterations - quite a bit more expensive. $230 is certainly not as bad. I still have my reservations as to the reliability of the process - last thing you want to deal with is some sort of internal short or a broken trace. 5 mil (or 6 mil which works just as well) looks much more reliable to me, but I may be wrong here. I started design with 6 mil rules, originally with a 256-part part, but since then I moved to 484-pin part. It's not too late to move to 4mil ...
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I still have my reservations as to the reliability of the process - last thing you want to deal with is some sort of internal short or a broken trace. 5 mil (or 6 mil which works just as well) looks much more reliable to me, but I may be wrong here. I started design with 6 mil rules, originally with a 256-part part, but since then I moved to 484-pin part. It's not too late to move to 4mil ...
They do 100% flying probe testing, so you can be sure that at least electrically they will be good. I can see the evidence of such test under microscope - there are dots on the pads where probe touched them.
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They do 100% flying probe testing, so you can be sure that at least electrically they will be good. I can see the evidence of such test under microscope - there are dots on the pads where probe touched them.
On your pictures it looks very good, at least for outer layers.
It gets worse with 484-pin parts. Balls are getting bigger and require 20-mil wide pads (as opposed to 16-mil for yours). So, it is only 4 mil between pads and traces. Xilinx even suggests 3 mil, but this is a miscalculation.
But bank 15 is 10-row deep. Sticking 2 traces between balls would save a lot of work ...
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On your pictures it looks very good, at least for outer layers.
It gets worse with 484-pin parts. Balls are getting bigger and require 20-mil wide pads (as opposed to 16-mil for yours). So, it is only 4 mil between pads and traces. Xilinx even suggests 3 mil, but this is a miscalculation.
But bank 15 is 10-row deep. Sticking 2 traces between balls would save a lot of work ...
If you open my gerbers, you will see a fair amount of 0.1 mm (3.9 mi) traces and spacings under BGAs, even if in some cases it didn't have to be that way. I did some random electrical tests of these traces, and there was no problems - shorts or opens. Not that I don't trust manufacturer's test, it was more of my way to shut up internal sceptic in me ::)
The point is - if and when I will come around to designing another board of similar caliber, I will have absolutely no qualms going for 0.1/0.1 mm trace/spacing. It is too big of enabler to pass up to. Just try it out yourself and you'll see why I think that way.
Oh - and another practical consideration. This was the first fab I used that managed to manufacture solder stops between pins of QFNs with 0.4 and 0.5 mm pitch, as well as between pins of 0804 4-resistor arrays - and in some cases these stops are just 0.1 mm wide! This is a BIG help for soldering, as you no longer have to be super precise with solder paste dispensing. For example, yesterday during assembling power supplies part of this board I accidentally moved stencil and smeared some solder paste so that it looked more like a line along QFN pins, but it was late in the evening so I decided to give it a try without fixing (normally I'd fix this with sharpened toothpick under microscope). After reflow it came out perfect, with zero bridges - and all of that thanks to solder stops! Even though one of QFNs (tiny 3x3 mm DC-DC converter TLV62130) came out a bit misaligned - still zero shorts.
So getting small traces right is good, but getting quality solder mask is equally important - especially if you will be assembling boards by hand. Also I ran one board through two full-duration LF reflow profiles - and solder mask didn't change color (like SM on many cheap boards tend to) - I couldn't tell it apart from fresh board. Like I said, I'm very impressed by the quality - not just in copper, but overall manufacturing. It's kind of hard to show in photos - it just "feels" right. Maybe they will screw me over one day - but until that day comes, I give them a benefit of the doubt.
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Well it looks like I will have to give them another order much sooner than I expected :( I just realized that I've made a FAIL of EPIC proportions which rendered board unusable!! |O
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Here's my PCB report:
Company: Uniwell
Sections: final inspection report, e-test report and microscopy report.
Yes, mine's the same, except I've got one more page with "Polar" logo on it with impedance tests results.
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Well, at least I'm able to test power supply part of the board, and it seems to work OK. Attached are some micro photos of QFNs. As you can see, TPS soldered just perfectly, while tiny TLV is a bit offset, but no shorts thanks to solder stops.
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So I've placed an order for the second revision of the board. Will post some photos once I receive them in about 1.5 weeks from now. :popcorn:
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So I've placed an order for the second revision of the board. Will post some photos once I receive them in about 1.5 weeks from now. :popcorn:
What was the problem with the first one (if not a secret, of course)?
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What was the problem with the first one (if not a secret, of course)?
I forgot to re-connect split power planes back to power rails once I actually split them |O Two rails (+3.3V and internal reference ground) were left unconnected. Stupid mistake :-BROKE I can't seem to get over the curse of first revision - every time I make a new board, I make some idiotic mistakes that makes rev 1 unusable. At least I became very good at detecting these mistakes before I start assembling boards :-DMM This is a consistent trend - as I finalize the board, I get too excited and cut corners on verification before ordering boards. Most of the time these are really stupid things like wrong pin numbers, or incorrect footprint, or big parts (usually connectors) are too close to each other so that they don't fit together, or mixed up TX and RX pins, or connected FPGA's _N clock pin for the clock (single-ended clock need to connect to _P pin) - really simple things, but since I worked on the board, I can't see these things in a plain sight.
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I forgot to re-connect split power planes back to power rails once I actually split them
This is difficult to repair, although you could try to make connection through the component pins if you have any exposed and connected to these planes.
Things like this one happen to me too. I try to verify everything as much as possible, but ...
I wish you luck with the second try.
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This is difficult to repair, although you could try to make connection through the component pins if you have any exposed and connected to these planes.
One of those unconnected planes is DDR3 reference plane, so even if I manage to connect it somehow, it will screw up return path for sure. This is the biggest issue, all other things could theoretically be connected via scraping some soldermask off vias and soldering some jumpers to them ("theoretically" as there is A LOT of connection points).
Things like this one happen to me too. I try to verify everything as much as possible, but ...
Yea, but every time it's a new kind of mistake, so at least I don't repeat same mistakes over and over :-X
I wish you luck with the second try.
Thank you!
Funny that right at that moment I'm reviewing production gerbers they've sent me for approval after adjustments they've made during pre-production prep. Interestingly enough they've slightly enlarged 0.1 mm traces at the expense of spacing, in some cases spacing shrunk to ~0.08 mm. I suspect that they just enlarged all traces to account for slight over-etching which always happens when etchant gets a little bit under the mask. I had this happened to me as well when I was making boards at home - so in order to get reliable 0.15 mm traces, I had to swell traces for about 0.03 mm to get traced that are spot-on 0.15 mm.
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Looks like what they're trying to say that if you don't request "Impedance Control", you can get any stackup they want. If so, to get anything in particular you need to request "Impedance Control". Anyway, the price they have for their boards, given that you get the stackup you want is great.
To be honest I have a hard time imagining 6+ layer board project which doesn't have any high-speed traces. So to me this seems more like an academic discussion.
There are plenty of applications for multi-layer boards without high-speed traces. One work project I had was a 30+ channel power supply unit with a total current input of around 125 A and was quite constrained for space. Had an 8 layer board.
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Ordered from WELLPCB 10pcs: 2L, 20 x 14.4 cm, lead free hasl, blue resist ($63) and 100pcs: 2L, 18.6 x 7.7 cm, ENIG, matte blue ($200), includes 0.5 mm pitch parts. Cheapest I've ordered so far, shipping is somewhat expensive though - $135 for fedex. Stencil quotation was very expensive for Chinese PCB service, $100 + additional $75 to shipping :scared:. IMO quantity is big enough to see how good and consistent they are. Also there was $25 tooling cost included for first pcb and $27 for second. So probably is will be complete peanuts ordering second time. Interestingly WELLPCB offered this:
2. Based on the confidence of our quality, as you can see from our web, customers can make payment after receiving the PCB prototypes(5~10 pieces). As the quantity you need is big, we can offer 50% in advance payment. Or if payment 100% in advance, we can discount the Paypal transfer fee.
Decided to try this because PCBwin was somewhat disappointing in quality lately. Electrically everything was fine but there were some cosmetic issues like some missing piece of copper on ground plane or scratch. And their quality was random when I ordered PCBA (10k U$) with one connector hand soldered on the edge (most issues with that). Half was carefully soldered and inspected. I found 2 fault marking stickers pointing to non critical soldering issues they likely forgot to fix and remove the sticker. Another half was like made on Friday by monkeys and not inspected at all :-//.
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Stencil quotation was very expensive for Chinese PCB service, $100 + additional $75 to shipping :scared:
Yep, I got $80 quote for stencil, so I ordered it at allpcb instead (took advantage of their $24 discount on shipping). Frameless polished with both sides on a same stencil ended up $33.44 with shipping and all other surcharges - unlike PCBWay, these guys don't cut out empty area of stencil and always ship the full panel which is rather heavy (hence the shipping cost - full price for shipping was $36).
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Yep, I got $80 quote for stencil, so I ordered it at allpcb instead (took advantage of their $24 discount on shipping). Frameless polished with both sides on a same stencil ended up $33.44 with shipping and all other surcharges - unlike PCBWay, these guys don't cut out empty area of stencil and always ship the full panel which is rather heavy (hence the shipping cost - full price for shipping was $36).
Well, I made a discovery. Apparently they are one and the same.
https://www.eevblog.com/forum/manufacture/allpcb-pcbway-yet-another-shell/msg1358453/?topicseen#msg1358453 (https://www.eevblog.com/forum/manufacture/allpcb-pcbway-yet-another-shell/msg1358453/?topicseen#msg1358453)
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Well, I made a discovery. Apparently they are one and the same.
https://www.eevblog.com/forum/manufacture/allpcb-pcbway-yet-another-shell/msg1358453/?topicseen#msg1358453 (https://www.eevblog.com/forum/manufacture/allpcb-pcbway-yet-another-shell/msg1358453/?topicseen#msg1358453)
While that invoice thing is unusal, they are in deed two differnent companys, two different fabs. The owners are friends, and i know it is unusal. The owners of PCBway helped Allpcb get started.
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@blueskull: How do you know WellPCB is the same as OurPCB? They look different to me. And the quality of OurPCB's boards on asmi's pictures appear to be better (to my eyes anyway) than the WellPCB's boards you have posted.
My PCB came with the same "certificate of completion" label, the same cross section sample, the same heat shrinking bubble wrap and the same foam.
Mine doesn't look that nice is because it uses 4 mil process and a lot of non-IPC standard, extremely small pads (for instance, my 0402 footprint is 0.6mm*1.0mm). My design is approaching their limit.
Also, via-in-pad without plugged vias look inherently nasty, but it works.
I received an invoice from wellpcb where issuer is Shijiazhuang OurPCB Tech. Ltd. So this confirms it without a doubt.
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My second revision boards are now on the way! Unless DHL screws things up again, I should receive them on Friday. Can't wait to see what else I might've screwed up :-BROKE
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slightly disappointed by ourpcb :
took 1 week to get my quote.
Took days to get the paypal account to transfer money.
took them days to finally find out that they can't source the bare material (rogers 4450 which is pretty standart)
an fianlly 24 hours to fully refund me.
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To be honest I have a hard time imagining 6+ layer board project which doesn't have any high-speed traces. So to me this seems more like an academic discussion.
The only 6-layer I've ever done was a high density LED array with drivers on the back. nothing fast, just dense.
(http://whitewing.co.uk/IMG_0269.JPG)
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After some delay caused by DHL, I've finally received my second order. Attached are scans of the board, more photos are in my blog post here: https://thingselectronic.blogspot.ca/2017/12/second-order-from-ourpcb-working-on.html
To my eye boards looks even better, note good quality of thru holes plating. Very impressed!
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Thanks for the hint @asmi. We've just ordered a couple of prototypes at them to test them.
Did any of those that ordered there or via wellpcb (this is where we ordered) managed to convince them that you'd like to pay invoice via bank transfer and not via PayPal?
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I received my boards. What can I say, wonderful PCBs. Perfect solder resist alignment, good silkscreen quality and alignment. Completely in different league compared to, say, pcbway or elecrow. It's really unusual to see cross section samples for cheap 2 layer boards :o. Seems I found my new supplier. From inspection report I found that material used is FR-4 IT158 which has 150oC Tg for which you usually would pay extra.
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I received my boards. What can I say, wonderful PCBs. Perfect solder resist alignment, good silkscreen quality and alignment. Completely in different league compared to, say, pcbway or elecrow. It's really unusual to see cross section samples for cheap 2 layer boards :o. Seems I found my new supplier. From inspection report I found that material used is FR-4 IT158 which has 150oC Tg for which you usually would pay extra.
Yea, these guys really surprised me (in a good way!) with solder mask quality, which is something I didn't expect at all, as the sole reason I've placed the order was great price for 6 layer boards. First of all - they are the only fab I ever used that managed to consistently produce 0.1 mm wide solder stops between pins - I got a lot of components on my boards with such thin stops (0804 resistor arrays, QFNs with 0.5 and 0.4 mm pitch), and each and every one of them is present - and it's bond to the substrate is strong enough that it takes some effort to peel it off. This has always been a hit-and-miss affair with the likes of PCBWay. And these solder stops are a huuuge help for soldering pain-in-the-neck QFNs and QFPs with exposed tab! Also I ran one of boards through 2 full-duration lead-free reflow profiles (to simulate reflowing top and bottom side components), and the mask didn't change the color at all - to the point that I couldn't tell that board apart from the fresh one. This is outstanding result!
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that finish is sick! I'm going to try them for my next 4L board
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Nice boards wraper. What finish did they apply?
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Nice boards wraper. What finish did they apply?
Looks like matte blue to me.
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Nice boards wraper. What finish did they apply?
Looks like matte blue to me.
yep
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did you just select "matte" for the finish? i tried with the online quote tool and it just say "matte", no colour
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did you just select "matte" for the finish? i tried with the online quote tool and it just say "matte", no colour
I ordered via email.
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Hello, in which cases do you guys select 2u instead of 1u for Immersion Gold finish ? Thank you. Got 0.4mm QFN's and tiny tiny filters, no BGA, single-reflow, nothing soldered by hand.
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Hello, in which cases do you guys select 2u instead of 1u for Immersion Gold finish ? Thank you. Got 0.4mm QFN's and tiny tiny filters, no BGA, single-reflow, nothing soldered by hand.
I think this is mostly needed for gold fingers. My board has 0.4 mm QFN as well, and it soldered OK:
(https://i.imgur.com/TaTqlHHl.jpg)
OurPCB had no problems manufacturing solder stops between pins despite them being just over 0.1 mm wide (you can see photos of my board in my blog).
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I think this is mostly needed for gold fingers.
ENIG is not suitable for gold fingers, only use on own risk where you don't expect multiple insertions. For gold fingers hard gold plating is used, it's completely different process.
https://www.eurocircuits.com/blog/gold-plating-for-edge-connectors/ (https://www.eurocircuits.com/blog/gold-plating-for-edge-connectors/)
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BTW, in case anyone is curious - I've assembled the board over weekend, discovered some more issues with schematics and footprints |O, but they are minor enough such that I was able to fix them right on the board by cutting a couple of traces and soldering in a jumper. I will post a more detailed update to my blog once I have enough time to write it up, also I need to write some HDL to test onboard peripherals, but I already tested the one thing I was worried about the most - which is DDR3L x16 module, and it works like sharm at full 400 MHz (800 MT/s) frequency even using full-strength FPGA drivers. This means that OurPCB made got controlled impedance traces very close to specs, as out-of-spec traces running at 400 MHz without termination would've certainly messed up signal integrity. I also have two 6G diff traces on board (from USB3-FIFO bridge to connector), as well as 4 HDMI diff pairs, so checking if they work will add confidence to specs, but like I said I need to develop HDL components to actually work with them.
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I gave them a try on an 8 layer with a few 0.8 mm BGAs and am reasonably pleased with the result. I'm waiting on some parts and expect to assemble next Wednesday. It showed up this morning by Fedex with a hand written label and no shipment notification.
They did some edits on the gerbers which they asked me to approve. Via pads were increased in size and some mask openings were increased. That did remove a few solder mask dams like on U90, but with OSP and lead free solder, it should be fine. In the future, I'll probably specify not to modify solder mask.
I specified ENIG, immersion silver or OSP for the finish (all the flat options). They quoted all three with OSP being $35 cheaper than the others.
I'm probably still doing production in the US, but it was nice to get in another prototype at low cost (about $300 for 10 versus $1800 for the US).
Edit: Forgot to add that they don't stock Isola materials. They asked to subtitute Iteq IT180 for the Isola IS410 I had specified. It's close enough and all the impedances were within 2% on their report.
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I gave them a try on an 8 layer with a few 0.8 mm BGAs and am reasonably pleased with the result. I'm waiting on some parts and expect to assemble next Wednesday. It showed up this morning by Fedex with a hand written label and no shipment notification.
I'm probably still doing production in the US, but it was nice to get in another prototype at low cost (about $300 for 10 versus $1800 for the US).
Thanks, this is interesting as I'm thinking of a project which would most likely require 8-layer board. Can you pls show the stackup you used for this design? It looks like "3 cores" to me based on a cross-section - is it so? Your SM offset looks a bit worse than what I had on my boards, but still fairly small if one considers the scale of the proto (U2 looks like DDR3 module, so 0.8 mm pitch part).
Also you use curious footprint to the right of R92 (and a couple at the bottom as well) which seem to have both thru-hole and SMT pads. Is the part really a combination of these, or it's a regular SMT part (VSSOP or TSSOP by the looks of it), and you need open thru-holes for some other reason (like testing, programming, whatever)?
Since I'm a hobbyist, ordering boards in US is absolutely out of question for me due to it being absurdly expensive, so these guys are the enabler as they allow me to make complicated boards without getting a mortgage to pay for production :)
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Thanks, this is interesting as I'm thinking of a project which would most likely require 8-layer board. Can you pls show the stackup you used for this design? It looks like "3 cores" to me based on a cross-section - is it so?
Yes, 3 3.5 mil cores (2x 106 weave glass each). The thickness is chosen so 4 mil inner tracks are 50 ohms and power planes are close to ground planes. The top prepreg gives 5 mils for 50 ohms. I've attached the stack from my fab notes.
In the dense DDR3 region:
top(1): signal
2: ground plane with no traces
3: 1.35 V plane with no traces
4: ground plane with no traces
5: signal with ground fill
6: signal with ground fill, cross traces on 5 at right angles, thick prepreg helps isolate too.
7: ground plane with no traces
8: signal with ground fill
Other parts of the Zynq have other voltage planes on some of the signal layers.
I probably could have done that in 6 layers, but this way I have no doubts about signal integrity.
Also you use curious footprint to the right of R92 (and a couple at the bottom as well) which seem to have both thru-hole and SMT pads. Is the part really a combination of these, or it's a regular SMT part (VSSOP or TSSOP by the looks of it), and you need open thru-holes for some other reason (like testing, programming, whatever)?
That part is an 8 terminal low ESL capacitor (Murata LLA21 series). The vias are part of the footprint so I don't have to place them for each one. They had openings for another board getting ENIG finish to avoid trapping chemicals and the fab house opened it up further.
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Yes, 3 3.5 mil cores (2x 106 weave glass each). The thickness is chosen so 4 mil inner tracks are 50 ohms and power planes are close to ground planes. The top prepreg gives 5 mils for 50 ohms. I've attached the stack from my fab notes.
In the dense DDR3 region:
top(1): signal
2: ground plane with no traces
3: 1.35 V plane with no traces
4: ground plane with no traces
5: signal with ground fill
6: signal with ground fill, cross traces on 5 at right angles, thick prepreg helps isolate too.
7: ground plane with no traces
8: signal with ground fill
Other parts of the Zynq have other voltage planes on some of the signal layers.
I probably could have done that in 6 layers, but this way I have no doubts about signal integrity.
I only used two signal layers (+ two reference planes of course, all internal) to route out DDR3L x16 (basically two DQ byte groups were on top of each other, and ADDR/CTRL spanned both layers). No SI issues noted even using full-strength FPGA drivers (didn't really need full strength for this board, but I tried it anyway in part to see how much of a margin design has). I was a bit concerned with using outer layers (along with internal) because signal propagation is faster on outer layers than it is on inner. Since I only have a Pro level license for Orcad PCB, it doesn't account for difference of propagation speed when doing trace length matching (I think I will need Allegro level of license to have this feature), as well as different z-length of layers - but that was something I could account to myself by setting offsets to traces based on which layer they go to). This all was probably overkill for DDR3-800, but I kinda prefer to learn doing things the right way from the get-go.
That part is an 8 terminal low ESL capacitor (Murata LLA21 series).
You learn something new every day :) Thank you again for your responses!
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I only used two signal layers (+ two reference planes of course, all internal) to route out DDR3L x16 (basically two DQ byte groups were on top of each other, and ADDR/CTRL spanned both layers). No SI issues noted even using full-strength FPGA drivers (didn't really need full strength for this board, but I tried it anyway in part to see how much of a margin design has). I was a bit concerned with using outer layers (along with internal) because signal propagation is faster on outer layers than it is on inner. Since I only have a Pro level license for Orcad PCB, it doesn't account for difference of propagation speed when doing trace length matching (I think I will need Allegro level of license to have this feature), as well as different z-length of layers - but that was something I could account to myself by setting offsets to traces based on which layer they go to). This all was probably overkill for DDR3-800, but I kinda prefer to learn doing things the right way from the get-go.
Xilinx says not to use the outer layers for DDR with the Zynq. I ignored that rule. I used Kicad and wrote a Python script to generate a trace length matching report which used individual propagation velocities for each layer and accounted for the in package delays. It only took about 20 lines of code if you don't count the lists of nets for each group. The Zynq pinout isn't very good and seems to require more layers.
Of course, that same document with the DDR rules specifies 50 ps matching on I2C and the UART, so some Xilinx rules are best ignored.
My longest Zynq die to DRAM line is 220 ps (160 ps on DQ) and I'm running with no termination as that's significantly less than the rise time. Even the internal terminations on the DQ lines are disabled saving quite a bit of power. The DDR didn't change with the revision and looks fine on the scope. Rise and fall is about 500 ps (scope and probe is 120 ps).
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I gave them a try on an 8 layer with a few 0.8 mm BGAs and am reasonably pleased with the result. I'm waiting on some parts and expect to assemble next Wednesday. It showed up this morning by Fedex with a hand written label and no shipment notification.
Yow, that mask registration looks pretty terrible. It's as if your pads are SMD on one side and NSMD on the other...
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I gave them a try on an 8 layer with a few 0.8 mm BGAs and am reasonably pleased with the result. I'm waiting on some parts and expect to assemble next Wednesday. It showed up this morning by Fedex with a hand written label and no shipment notification.
Yow, that mask registration looks pretty terrible. It's as if your pads are SMD on one side and NSMD on the other...
Really? It looks to be fine to me. It doesn't cover the pads at all.
Solder mask regsitration is typically +/- 2mil (0.05mm) which is why soldermask is normally specified as 2mil larger than the pad.
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Really? It looks to be fine to me. It doesn't cover the pads at all.
Solder mask regsitration is typically +/- 2mil (0.05mm) which is why soldermask is normally specified as 2mil larger than the pad.
Yea I don't see any issues as well. Microphotos can often be very deceiving because it's not easy to "feel" the scale. Even when I look through stereo microscope with my own eyes, I sometimes have to put some kind of "known" object into the field of view to really "feel" the scale. If you look at your very own finger under x20 stereo microscope, it's not easy to figure out that it indeed is a finger, because it looks more like a mountain ;)
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I had much better alignment on PCBs with 0.5mm pin pitch ICs and ENIG, and about like this on cheaper PCBs with a bit larger parts and lead free HASL. In any case this is order of magnitude better alignment compared to what you'll get from pcbway.
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I think it looks bad because the solder mask opening on these capacitor holes is about 2mil smaller than the copper ring (1mil from each side). The solder mask is shifted South-West 1.5 - 2mil, which cause the North-Eastern side to be completely covered, which looks weird.
On the pads, where solder mask opening looks about 4mil wider than the pad (2mil from each side), it looks very good. You can see a gap between the pad and solder mask on all sides. Which means that the solder mask misplacement is less than 2 mil.
Darrell has said that they extended solder mask openings. What was the gap between pads and solder mask in the original Gerbers and how much they extended it? I wonder why they didn't extend the solder mask openings on the capacitor holes?
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I think it looks bad because the solder mask opening on these capacitor holes is about 2mil smaller than the copper ring (1mil from each side). The solder mask is shifted South-West 1.5 - 2mil, which cause the North-Eastern side to be completely covered, which looks weird.
On the pads, where solder mask opening looks about 4mil wider than the pad (2mil from each side), it looks very good. You can see a gap between the pad and solder mask on all sides. Which means that the solder mask misplacement is less than 2 mil.
Darrell has said that they extended solder mask openings. What was the gap between pads and solder mask in the original Gerbers and how much they extended it? I wonder why they didn't extend the solder mask openings on the capacitor holes?
The original gerbers had 50 um (2 mil) each side mask to pad clearance. They didn't change that, just increased the opening where there is was an exposed via. The mask is shifted almost 2 mils. Much more and they would have needed to redo it, but it will be fine. I've seen worse from far more expensive board houses. The drills are shifted a few mils in the opposite direction.
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The original gerbers had 50 um (2 mil) each side mask to pad clearance. They didn't change that, just increased the opening where there is was an exposed via. The mask is shifted almost 2 mils. Much more and they would have needed to redo it, but it will be fine. I've seen worse from far more expensive board houses. The drills are shifted a few mils in the opposite direction.
Speaking of drills, what size did you use for breakout area? I used 0.2 mm drill and 0.45 mm pad vias, but I wonder if someone tried using smaller ones. It would be cool if it would be possible to somehow fit two traces between breakout vias for 0.8 mm pitch part, but I suspect that's going to require via-in-a-pad or microvias. Although dynamic unused pads suppression (removing unconnected pads for vias from internal layers where there is no connection to them on that layer) could help with that as this way you will only be limited by drill-to-copper constraint.
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Yea I don't see any issues as well. Microphotos can often be very deceiving because it's not easy to "feel" the scale. Even when I look through stereo microscope with my own eyes, I sometimes have to put some kind of "known" object into the field of view to really "feel" the scale. If you look at your very own finger under x20 stereo microscope, it's not easy to figure out that it indeed is a finger, because it looks more like a mountain ;)
Here's the previous revision, made in USA for about $1600. As you can see, it's a bit worse. Those soldered just fine. Both boards look fine to the naked eye or even with a loupe. My photo setup is about 6.4 um per pixel (Canon SLR with 100 mm f/2.8 macro).
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Speaking of drills, what size did you use for breakout area? I used 0.2 mm drill and 0.45 mm pad vias, but I wonder if someone tried using smaller ones.
0.46 mm pad, 0.2 mm drill. I don't think OurPCB is had good enough drill registration to get two traces between vias on 0.8 mm. Xilinx does it on some eval boards, so it can be done.
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0.46 mm pad, 0.2 mm drill. I don't think OurPCB is had good enough drill registration to get two traces between vias on 0.8 mm. Xilinx does it on some eval boards, so it can be done.
If you remove unused pads, you will have 0.6 mm drill-to-drill, but even if you reduce it to 0.5 mm (to allow ±0.05 mm drill positioning tolerance) that still is enough to put two 0.1 mm traces and three 0.1 mm spacings.
I will try this on my next design that's going to have 32 bits wide memory bus so chances are I will need any routing space I can get.
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0.46 mm pad, 0.2 mm drill. I don't think OurPCB is had good enough drill registration to get two traces between vias on 0.8 mm. Xilinx does it on some eval boards, so it can be done.
If you remove unused pads, you will have 0.6 mm drill-to-drill, but even if you reduce it to 0.5 mm (to allow ±0.05 mm drill positioning tolerance) that still is enough to put two 0.1 mm traces and three 0.1 mm spacings.
I will try this on my next design that's going to have 32 bits wide memory bus so chances are I will need any routing space I can get.
The problem is 0.2 mm is the finished via size. Most shops drill that with an 0.25 mm bit to allow for plating. I think OurPCB likely used an 0.3 mm on mine as the holes are bigger than the last revision (confirmed from cross section photo measurements). They were off by as much as 0.08 mm (measured) on drill positioning with my board. I think you would have to go with 0.075 mm traces and spaces to do it as Xilinx did and you might still need a better boardhouse. I'd probably go for more layers instead. I wish these parts were 1 mm pitch for that purpose.
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The problem is 0.2 mm is the finished via size. Most shops drill that with an 0.25 mm bit to allow for plating. I think OurPCB likely used an 0.3 mm on mine as the holes are bigger than the last revision (confirmed from cross section photo measurements). They were off by as much as 0.08 mm (measured) on drill positioning with my board. I think you would have to go with 0.075 mm traces and spaces to do it as Xilinx did and you might still need a better boardhouse. I'd probably go for more layers instead. I wish these parts were 1 mm pitch for that purpose.
I think I'm gonna give it a try anyways. Will see what happens :) Would be interesting how they handle that. Technically they are able to do 3 mil traces/spacing, so if above plan won't work, I will just make traces narrower.
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I've finally tested USB 3.0 communication via FT601. In single channel mode it achieved 323 MBytes/s (~2.5 GBit/s) of actual data bandwidth, which matches what FTDI says it should be, so I conclude that 5GBit transmission lines on the board work as they should, and it's impedance is right on the mark (multi-GBit lines are famous for very strict tolerances).
Also I gotta say that I really like this bridge chip - so simple to work with yet so powerful. If only it wouldn't cost as much as it is (and "consume" so many IO pins) I'd stick it to all my designs!
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I've finally tested USB 3.0 communication via FT601. In single channel mode it achieved 323 MBytes/s (~2.5 GBit/s) of actual data bandwidth, which matches what FTDI says it should be, so I conclude that 5GBit transmission lines on the board work as they should, and it's impedance is right on the mark (multi-GBit lines are famous for very strict tolerances).
USB 3.0 works even on 2 layer board without remotely adequate impedance and trace length matching. With one issue though, wireless mouses, keyboards and wifi perform erratically or just die nearby such thing when you, say, transfer files to memory stick.
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Really? It looks to be fine to me. It doesn't cover the pads at all.
Solder mask regsitration is typically +/- 2mil (0.05mm) which is why soldermask is normally specified as 2mil larger than the pad.
Yea I don't see any issues as well. Microphotos can often be very deceiving because it's not easy to "feel" the scale. Even when I look through stereo microscope with my own eyes, I sometimes have to put some kind of "known" object into the field of view to really "feel" the scale. If you look at your very own finger under x20 stereo microscope, it's not easy to figure out that it indeed is a finger, because it looks more like a mountain ;)
In case anyone is curious, here's that same area on the same board populated. The solder on the ugly QFN and 8 terminal capacitor turned out fine. Everything works and only one resistor value change was required in bringup.
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In case anyone is curious, here's that same area on the same board populated. The solder on the ugly QFN and 8 terminal capacitor turned out fine. Everything works and only one resistor value change was required in bringup.
Sounds like you just saved yourself enough money for 5 more iterations ;D
That QFN looks familiar... TLV62130? I use it on my board as pre-regulator for TPS65400 main PMIC.
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That QFN looks familiar... TLV62130? I use it on my board as pre-regulator for TPS65400 main PMIC.
Yes, TLV62130 for the 1.0 V rail.
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I'm about to order 3 different pcbs from that company.
Did someone use their assembly chain ?
I'd love to have both the pcb pro + assembly done at the same place.
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3 different PCB ordered from that company.
1st one received this week.
120 units in panels of 6.
Rogers 4003c, 4 layers, DFN10 and 0201 passive in.
the plus :
honestly impressed by the quality. Price is rather reasonable. Not the cheapest, for sure, but the best Q/P ratio I ever had.
The minus :
communication in English is not straightforward
they are not fast according to modern standarts.
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The minus :
communication in English is not straightforward
Could you please elaborate: did they encounter difficulties following your instructions? did they respond in a broken English so it was not clear what they meant?
I plan to try them out with some PCB fabrication and PCBA jobs, but communication (clear, and responding to *all* raised points in a timely order) is very high on my list - due to some past bad experience I had encountered with some other vendors.
P.S. I am totally not impressed with the SM and drill registration as seen in the pictures posted by Darrell, although they seem to be within IPC-A-610 Class II limits.
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I plan to try them out with some PCB fabrication and PCBA jobs, but communication (clear, and responding to *all* raised points in a timely order) is very high on my list - due to some past bad experience I had encountered with some other vendors.
I recently did PCBA with them. I would suggest to explicitly request wave soldering for through hole. SMT was flawless on all of my 500 boards. Around 45 SMT on components each, including 0.5mm pitch QFN. But through hole apparently was done manually with solder pot. Excessive flux residues and tons of touch up with solder iron.
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Could you please elaborate: did they encounter difficulties following your instructions? did they respond in a broken English so it was not clear what they meant?
My communication experience was completely different from sdouble.
I used WellPCB (PCB fabrication only, no PCBA). Whether they're the same as OurPCB or not is not clear, but the quote from WellPCB was much less than OurPCB wanted.
Communications were excellent. And quick too. No problems whatsoever!
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Whether they're the same as OurPCB or not is not clear, but the quote from WellPCB was much less than OurPCB wanted.
They are the same, and they said me so as well. Assembled PCBs from wellpcb I received last time came in boxes with OurPCB printed on them.
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But through hole apparently was done manually with solder pot. Excessive flux residues and tons of touch up with solder iron.
Thanks for the head up. I would have never thought that a mid-size(?) factory would hand-solder THD at Q=500 pcs.
My current design is 100% Through Hole, but very difficult to solder - large and thick board, 5 Oz copper. Some component leads extend only 1mm below the PS surface.
I can instruct my sales contact at the factory whatever I want, but at the end I may discover that either my comments have not been passed on to the factory, or that the shift engineer who got the email from the sales contact was not fluent enough in English to understand my notices.
The problem is that short of an annual factory visit, you never know how they assemble your board. While PCB fabrication and inspection is a fairly automatic process, PCBA is not, and we are at the mercy of incompetent laborers who lack training or basic professional common sense.
ISO9001 means nothing if that paper-flow process standard does not demand English proficiency tests for factory engineers or shift foremen.
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I did produce 4 boards in the last weeks from OURpcb. Rogers 4003c, 4 layers, and FR4 Tg=180, 2 and 4 layers.
First of all, you always communicate with the same human being. This is generally speaking nice .. except when she has days off for instance. Then you have to wait.
Second, I had to reformulate several requests due to clear misunderstanding. However, all situations were solved eventually. Sometimes it took days to solve basic problems like panel arrangement for instance.
However, i must confirm that the quality of the boards is by far higher than what i was used to.
The minus :
communication in English is not straightforward
Could you please elaborate: did they encounter difficulties following your instructions? did they respond in a broken English so it was not clear what they meant?
I plan to try them out with some PCB fabrication and PCBA jobs, but communication (clear, and responding to *all* raised points in a timely order) is very high on my list - due to some past bad experience I had encountered with some other vendors.
P.S. I am totally not impressed with the SM and drill registration as seen in the pictures posted by Darrell, although they seem to be within IPC-A-610 Class II limits.
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Just received another board - this time ordered through WellPCB, also 6 layers, but it only was $195 USD including shipping (last time it was $230). This time they didn't include cross-section sample nor QA report, but actual board quality is still excellent!
Front side:
(http://i.imgur.com/QmH8a4fl.jpg) (https://imgur.com/QmH8a4f)
Back side:
(http://i.imgur.com/FZ94TBgl.jpg) (https://imgur.com/FZ94TBg)
FPGA footprint:
(http://i.imgur.com/qkq2pWcl.jpg) (https://imgur.com/qkq2pWc)
DDR3L x16 footprint:
(http://i.imgur.com/ayMgG4cl.jpg) (https://imgur.com/ayMgG4c)
Main PMIC:
(http://i.imgur.com/7rwmSlfl.jpg) (https://imgur.com/7rwmSlf)
Expansion connector:
(http://i.imgur.com/m4yufscl.jpg) (https://imgur.com/m4yufsc)
HDMI connector and ESD protection chip:
(http://i.imgur.com/Ujlozocl.jpg) (https://imgur.com/Ujlozoc)
Hopefully will assemble the board over the weekend to see if it will work. But so far it looks amazing!
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I've assembled the board and it's working!
I did gain a couple of gray hairs though during assembly - once I reflowed the board, +5V input power rail was shorted to ground! :wtf: I traced the problem to the PMIC chip since some other pins were also shorted. After several attempts to resolder pads without removing the chip, I've concluded that the problem is with the chip itself, so I needed to replace it. This was a moment I regretted using lead-free paste as removing the chip (it's QFN-48) was quite a chore since my board had two full internal ground planes and so could take A LOT of heat - and I didn't have preheater (now it's on my shopping list). Once I took it out, I decided to use regular leaded solder for a new IC. That was much easier and faster of course.
After that I've accidentally applied power backwards for few seconds until I realized that :palm:. Once I reversed the power, only two out of 4 rails came online. Fearing for the worst (that I blew that chip too), I decided to touch up all QFN pins once again with an iron and see if that helps. And IT DID! All power rails came online and I saw "power good" LED came on.
Once the power issue is resolved, I've verified that Vref on JTAG connector is what it should be (to make sure I won't blow up the programmer) I connected programmer and plugged it all to computer. And Vivado recognized the chip!!! :phew:
There are two interesting things about this board. First of all, it included a single 512 MBytes (256Mx16) DDR3L chip, which has its "chip select" line permanently grounded as otherwise there are not enough pins in a single IO bank for ADDR/CTRL lines. I've quickly built a test design with DDR3 controller and Microblaze CPU to confirm that memory works, and indeed it did work! Second interesting thing is using 1.8V QSPI flash IC - I wanted to check if it's possible in principle to build a system without 3.3 V rail at all to save on DC-DC converters. And it turned out that it's entirely possible, so that if all your peripheral chips can work at 1.8 V, you can get rid of an extra DC-DC for 3.3V rail. There are a couple of gotchas though, so if you want to build such system - make sure you use schematic checklist spreadsheet provided by Xilinx to verify all your connections! I do have 3.3V rail on this board as I use it for HDMI stuff, and there is an option to set IO voltage for one of extension connectors, but both banks 0 and 14 (where configuration-related pins are) are completely devoid of anything 3.3V.
Finally, this is the first more-or-less complex board of mine that actually works on a first revision! :-DD
In case anyone's curious, here is a schematic of this board: https://1drv.ms/b/s!AkGeV4xlumxjg84U2EyEBlXt-h4mQQ