Nobody else mentioned making the apertures SMALLER than the pads. The smaller the components and lead pitch, the greater a reduction should be applied to the pad area to give the aperture area in the stencil. I do use .003" (roughly .075 mm) thick stencils, but ALSO reduce the apertures to about 75% for SOIC ICs, and even smaller for finer pitch chips.
Jon
That is a savagely thin stencil and a very aggressive aperture reduction, however there's way more to fix for the OP before starting to optimise stencil apertures.
A decent paste applied properly with 1:1 aperture ratio should still look like a decent print with sharp edges, and that print should stay that way for hours if left in the rack. The OPs print is awful before reflow even takes place, aperture reduction isn't the solution if they haven't got their printing process at least good enough that it looks like a nice print even if there is too much paste height.
We typically only apply weird stencil aperture shapes or reductions if we know there's something odd about the footprints and how they relate to the actual devices. Most of the time 1:1 is exactly what works in a tensioned stencil, a reduction helps for unframed but I would still expect a better result than that when I am forced to use one.