7.5digit diy voltmeter?

[Kleinstein]

I have build an integrating ADC around an µC some time ago - though not very high performance.  I am currently actively thinking about a better way.

I don't see a principle problem it getting really good linearity without special ASCIs. Much about the special parts in the 3458 is about getting high speed. The one point I have a hard time to estimate so far is jitter and variations in charge injection with the switches. However these are more factors effecting noise and would hardly effect the linearity. The important factors for the good linearity of the 3458 are likely the good resistor(s) inside U180 (it is mainly one critical resistor), maybe the stable resistor ratio if no corrections are used and the high speed integrator, that allows the use of a small integrating cap. Long integration time can to a certain degree compensate for a larger cap.

I see a chance that one could get a comparable linearity and comparable (or even lower) noise at low speeds. Leaving out the high speed modes would make things a lot easier. However for conversion times of less than about 1 ms, there are attractive ready made ADC chips. There is no more need to use the same ADC for precision DC / low frequency and the high speed (e.g. true Volts).

The design I am currently planing is kind of similar to the 34401 hardware, but with still a classical rundown phase. If there is no layout caused trouble, I would expect a linearity similar to the 34401 (the first version would be limited by a cheap resistor though) and a considerably lower noise. As the HW is relatively simple it would be at least a good starting point for a few experiments. So far I have a crude layout (with still a few air-wires) and the software still needs debugging and the ASM coding for the adjustment measurements is still missing.

[HalFET]

Mine is currently living upside down on a piece of copper clad 

Mhh, if you sacrifice speed it's indeed doable, but at that point you could also start averaging with highspeed delta-sigma converters.

[Kleinstein]

In my design,  limitation due to the µCs speed are not that severe. It is mainly during the rundown phase, that using software limits the time resolution for the comparator to about 200-400 ns. This kind of adds a little (maybe 5-50 µs) to the length of the rundown phase, but the final step and thus the noise relevant part would be ADC. So chances are still to have a reasonable fast rundown - so far I plan for something in the 100µs range. It will still be possible to use a kind of dual slope mode with 50 µs integration and 100 µs rundown - but this already looses 2/3 of the time to the rundown phase and is thus less attractive.

For the run-up phase it is the integrator hardware that limits the speed, at least with a simple 2 or 3  pattern type feedback. It is only the more complicated feedback modes based on timing that might like to have a faster µc.

So far I use code speed for timing and I am thus limited to ASM programming - this kind of makes it unattractive to do more complicated calculations in the µC at the ADC. So much of the math of scaling the result would be done in the ground referenced part (the PC for the beginning).

Averaging with a higher speed sigma delta ADC does not help with the large range INL and would still keep the small voltage range. If used with some dithering it could help with some odd points, so more like an improvement in DNL.  I would consider the higher speed sigma-delta (or high resolution SAR) converters more like an alternative for the high speed range, like < 100 µs, where the integrating ADC is usually not that good. So I so need to implement a super fast mode for the multi-slope converter. For me the main target would be a 20 ms integration time - the slightly fast range is not that attractive anyway and longer times could use averaging.

[pigrew]

Related to the timing, you can usually use the micro's timer module. For example, I'm currently working on a project to measure timing of pulses, with a resolution of about 15ns (on 8 independent channels), using a Tiva C processor. Of coarse, the micro's internal PLL adds jitter. I think the motor PWM modules may also be advantageous due to their ability to change an output based on an input.

[Kleinstein]

I know one could also use the timer HW in the µC. The problem is however this will add to the response time - it is more like a problem of response time, not so much resolution. The important part is accuracy in the output timing - no high resolution is needed.
The main advantage of a more accurate response to the comparator during the run-down would be with the coarse slope. An error in ending the fast slope would result an an about 10 times (depending on the ratio of the slopes) longer extra time needed for the slow slope, thus an 1 µs error would give an extra 10 µs for the slow slope. The end of the slow slope might show uncertainty due to noise anyway - so the advantage of a faster comparator here is limited. The ADC can still resolve a little more, as the ADC operates at a lower bandwidth than the comparator.  This reduced bandwidth is an advantage of the extra ADC, that comes essentially for free with an µC.

Ignoring other noise sources, resolving 1 µs  (fast run-down) after 20 ms gives 4.5 digits of resolution. With a slope of 1/10 the speed this would be 5.5 digits and with an ADC that can resolve 10 or 100 times finer would be a resolution limit of 6.5 or 7.5 digits after 1 PLC. So this limit should not be a significant limit for a simple, more low cost ADC circuit. Ideally the rundown would need up to about 1.5 periods of the run-up modulation (e.g. 5-50µs) plus something like 10-20 µs for the slow slope and another 10 µs for the ADC sampling.  So chances are still there to have a rather fast rundown phase. A more accurate comparator and timing would really help with a slower slow slope, in case more than 7 digits are needed. For the time being I don't see a problem here.

I am current planing with an AVR (mega48 or similar) at something like a 16 MHz clock. Not having a PLL for the clock could mean I might get away without an extra flip-flop for synchronization. I still have not decided on the type of feedback during run-up. For the first test it will be the simple 2 pattern type because it is about the simplest solution.

[HalFET]

Since I don't really have the current version drawn out I'll just explain my current system. The integration capacitor is a through hole film capacitor standing over the opamp which is feeding it, there's a "low sample rate" flash ADC in parallel with it which feeds directly into the FPGA (Spartan 6 dev board), and two zero crossing detectors. The system clock is 10 MHz from an external Rubidium disciplined TXCO that I still had laying around. Reference is a LM399 feeding the "ADC" through a Caddock ceramic hybrid divider and is buffered/mirrored.

• "Auto-zero" at start of every conversion cycle. (ADC connected to ground) and a quick dual slope conversion
• Select charge resistor based on continuous input monitoring from a separate flash ADC.
  
• Integration for 100 clock cycles
• Based on charge collected (monitored using the flash ADC measuring the capacitor) switch to a known discharge current, goal is to achieve discharge in sub 40 clock cycles.
  
• On zero crossing detect switch to a charge current proportional to remaining charge (since there will be overshoot), and do a run up until next overshoot.
  
• Repeat until remaining charge is sufficiently low.
  

Even with the FPGA running the show and it's asynchronous response "hardware" you still have noticeable overshoot actually. Total conversion time is in the range of 50 microseconds at the moment (at the most), if I push it further I run into limitations with my current FETs for switching, I last stopped at attempting to measure the charge injection caused by different transistors at different voltages but I'll have to change tactic for that since my current results aren't reliable enough.

In short: I get 5.5 digits reliably with the current topology at its full sample rate, and 6.5 depending on the position of the moon and the sample rate.

[MisterDiodes]

...I would suggest you add this to your reading list to see how these projects were done over 37 yrs ago.  Written by Jim Williams for NSC in 1981 (long before NSC being taken over by TI) here's a prototype  inspiration app-note schematic for a discrete 20-bit ADC, dual slope converter that works surprisingly well - and without an FPGA (a slow CPU will still work).  You could probably push this to 21~23 bits with modern components and LTZ Vref.  Notice the tricks to make a fast precision comparator (at A2 and A3):

http://www.ti.com/litv/pdf/snoa597b

Just because it's old doesn't mean the methods don't work today.

Also take a look at Art of Electronics 3rd edition to see a comparison of how a 3456a and 3458a are designed (and how you can use a modest ADC to get great results), and look at what has to change going from 6.5 bits to 8.5 bits.  It is not trivial.

I think the mind-set stumbling block some designers face is only trying to use a single method or ADC chip for a good design solution - sometimes using discretes and multiple approaches is better than a thinking about a single chip (if you've got room).  The most common "gotcha": If you're talking about using diffused resistors on an IC die then the common limiting factor of being useful is the overall noise of the ADC or DAC - it's not the "bits resolution" when you're after long term stability and low noise.  "Real" stable resistors (PWW and some extent foil) will always be less noisy than any resistor on a die - at the expense of much more real estate required.

As far as constructing a DIY 7.5 digit meter:  As a learning tool it will be sort of fun to see how quickly it can become frustrating to find out how reality and noise work - but only as long as you're having a good time along the way.  In terms of just getting a -good- low cost meter you might as well get a used working 3456a for a few hundred $$, or if you can afford it a used working 3458a and be miles ahead in cost and time savings for a 8.5 digit meter.  If you include the cost of building the decent DMM front ends, at low-noise, accurate >>10Gohm input impedance (that itself is a project) - a useful, reliable meter that's accurate and stable at low PPM error won't ever be "dirt cheap".  But certainly it's a fun journey of discovery to find out "why" that is.

[Mickle T.]

This is a cheap and simple DIY 8.5 digit voltmeter I made for fun a few years ago (after the some 7.5 digit ones). Unfortunately, I can only show a draft/cuted version, but I think everything is clear.

[Kleinstein]

...I would suggest you add this to your reading list to see how these projects were done over 37 yrs ago.  Written by Jim Williams for NSC in 1981 (long before NSC being taken over by TI) here's a prototype  inspiration app-note schematic for a discrete 20-bit ADC, dual slope converter that works surprisingly well - and without an FPGA (a slow CPU will still work).  You could probably push this to 21~23 bits with modern components and LTZ Vref.  Notice the tricks to make a fast precision comparator (at A2 and A3):

http://www.ti.com/litv/pdf/snoa597b

Just because it's old doesn't mean the methods don't work today.
....

That old Design is completely different from modern high resolution ADCs in relying on a linear slope for a capacitor to charge at a constant current. So it is really limited by the quality of that cap, that in addition needs to be relatively large. In addition I would expect it to be kind of noise sensitive. AFAIK a similar design is considered in image sensors, using one good slope for simultaneous converting hundreds of signals. It is not even a classical dual slope, more like a variation a of single slope with extra cal cycles.

I totally agree that is will not be cheap to build a DMM - the ADC is just a rather small part, and one point that really needs the experience is to have it work reliable so you can trust the values. While semiconductors got rather cheap, the high quality resistors are still pretty expensive.  I don't think there is much to worry about excess noise from thin film resistors, even at a 8 digit level - especially with the more modern way with more like short integration at a time and averaging afterwards, it is not that sensitive to 1/f noise any more.

The SD chips usually don't use resistors, but switched capacitors. Still they have a limitations due to small charges moving around. This way they also get surprisingly energy efficient.

@HalFET
Getting a 5 digit resolution from a single rundown process is already quite good. An important factor for the high resolution in the multislope converters used in the DMMs is having the signal integration and the counteracting references to be active at the same time. This way they get something like an extra 3 digits before the final rundown.

[HalFET]

Of course it ain't trivial, if it was everyone would be doing it... Especially as hobbyist it's fairly difficult, they spent years working on some of these things with entire teams. For example that design you linked is fine, but if you actually try to implement it you'll see there's a lot more to getting the actual performance out of it. (I tried it myself actually.) Plus just copying someone else's circuit is boring if you're not being paid for it!

But indeed, the entire point of the analog design is getting the noise floor low enough and keeping everything stable, precision components aren't strictly required actually! The clearest example of this can be found in some of the older Keithley circuits, fairly common average components which are easy to source, but they were selected for characteristics that weren't necessarily listed on the datasheet. Additionally the 3458 in some ways is actually a clumsy design if you think about it, the converter ain't that intelligent, they went for specially binned components, ...

But why do people keep thinking they need the LTZ1000 for this? It's an overkill reference for many applications, especially for 6.5 and 7.5 digit meters. It increases your BOM cost while you won't really have any significant gain from it in most cases, since I seriously doubt I'd be able to design something that can do actual 8.5 digit conversions reliably on my own. And most people who think they can do it are probably over-confident (no offence intended to Mickle T. - his design might be able to do it).

@Kleinstein:
Thanks, I was quite proud when it worked! I wonder how those daft bastards at Keysight got it working with a C0G cap though. But the main performance increase actually came from improving the comparator, its what made the multi-slope conversion feasible.

[Echo88]

Very impressive Mickle T!

[Inverted18650]

Following. thank you to all the members contributing. I find myself becoming fascinated with *metrology

[MisterDiodes]

HalFET:  Careful now, don't get too over confident:  Those daft bastards at HP (decades before Keysight) that made that clumsy design - those are my people that I worked with helping build some of their chips.  And the end result is the single most successful and profitable  DMM ever produced.  So in that sense of making money:  they actually came up with a darned good product.  I don't see anything that good from Keysight recently, so you might have a point 

Kleinstein:  Yes that's an old design and I wasn't suggesting anyone rush out to build one - the idea was that those concepts can be improved with newer components, and the design concept serves as a learning tool.  And "yes" you can build one at > 20 bits (we did so for years) and "no" that integrator cap -value- isn't as important as you'd think...but it still must have low DA which is clearly pointed out in the text.  Teflon or Polystyrene will work...maybe polyprop in a pinch.  The design still relies on a low noise Vref.

Clarification: - when I was pointing out be careful resistors on chip scale ADC's and DAC's - I was not referring to those units with thin film (those will be larger resistors, maybe laser trimmed, and usually some sort of sputtered chrome-variant or similar).  I was talking about ADCs/DAC with diffused resistors on board (as in diffused / ion implant / epitax etc.) .  You'll usually find these on ADC's with differential input front ends with PGA and/or scaling resistors - watch out for much higher noise and higher TC than you might want.  Or high resolution DAC's that are fairly dismal for noise.  In those cases using real resistors will get you quite a bit lower noise - at the expense of real estate.  Look at the datasheets for TC / noise and you'll know.  For instance look at <10Hz noise on an AD5791.

It depends on what you're after for performance, and budget of course.  There is no correct answer that fits every need.

MickleT:  Thanks for posting the design concept.  With all due respect I might not call that an "8.5 digit meter" in the sense that I think the original poster might be referring to an actual DMM maybe (That might include an accurate high impedance front end range selection for maybe more useful input voltage measures, maybe a display, etc.) but we get the idea on the ADC section - just using discretes you demonstrated a reasonable  ADC solution!  Neat!

[David Hess]

...I would suggest you add this to your reading list to see how these projects were done over 37 yrs ago.  Written by Jim Williams for NSC in 1981 (long before NSC being taken over by TI) here's a prototype  inspiration app-note schematic for a discrete 20-bit ADC, dual slope converter that works surprisingly well - and without an FPGA (a slow CPU will still work).  You could probably push this to 21~23 bits with modern components and LTZ Vref.  Notice the tricks to make a fast precision comparator (at A2 and A3):

http://www.ti.com/litv/pdf/snoa597b

Just because it's old doesn't mean the methods don't work today.

This design has lessons to teach in what not to do for a precision ADC intended for real world measurements.  It is a single-slope instead of dual-slope converter meaning that it has the following fatal disadvantage:

4. Unlike a dual-slope, this converter has no inherent noise rejection capability. The EX input signal is directly coupled to the comparator input with no filtering. This is a decided disadvantage because most “real world” signals require some smoothing. If a filter was placed at the input substantial time lag due to settling requirements would occur. This is unacceptable because the converter relies on short time intervals between multiplexer states to effectively cancel drift. The solution is to use the microprocessor to filter the signal digitally, using averaging techniques.

Its input integration time is variable and depends on signal level so it has no normal mode rejection to remove power line interference.  This will limit its resolution to 5.5 to 6.5 digits or less (based on various modern meters operating under the same constraint) except in specialized instrumentation applications where power line interference is not a consideration.  I suspect National used it for automatic test equipment in a very controlled environment or maybe one of their customers did.

[David Hess]

I wonder how those daft bastards at Keysight got it working with a C0G cap though. But the main performance increase actually came from improving the comparator, its what made the multi-slope conversion feasible.

Some C0G/NP0 capacitors are pretty good as I discovered designing sample and holds.  I was surprised when I ran across old run-up dual-slope converter designs which used silver mica capacitors.  After that, I wondered why anybody was using dual-slope converters with picky capacitors at all.  Maybe nobody could understand how the run-up dual-slope converters worked because application notes from Siliconix were so poor; I am not convinced now that even they understood them.

[MisterDiodes]

... I suspect National used it for automatic test equipment in a very controlled environment or maybe one of their customers did.

Yup - Like when you have to measure 60Hz signals and -can't- filter out power line freq....because that's the signal.  That turned out to be a real application.  One customer being HP.... 

... and like I said app note is a teaching tool - -not- - a finished schematic.  Of course Dual Slope methods can result in lower noise - and how do you think you'd modify this concept circuit? A Dual slope strategy would be the next logical step in trimming down noise.

[David Hess]

... I suspect National used it for automatic test equipment in a very controlled environment or maybe one of their customers did.

Yup - Like when you have to measure 60Hz signals and -can't- filter out power line freq....because that's the signal.  That turned out to be a real application.  One customer being HP.... 

Then you either add a precision sampler or rectify the AC before measurement.  More recent multimeters going back to at least sometime in the 1990s are apparently using precision samplers for AC measurements which is nice because you get free AC RMS and AC+DC RMS with that.

But if normal mode rejection of power line interference was not a problem, then instrumentation ADCs would not routinely and deliberately include sin(x)/x response which notches power line interference out.  Nobody would use dual-slope ADCs if single-slope ADCs could be used instead.

... and like I said app note is a teaching tool - -not- - a finished schematic.  Of course Dual Slope methods can result in lower noise - and how do you think you'd modify this concept circuit? A Dual slope strategy would be the next logical step in trimming down noise.

I would modify the single-slope circuit by turning it into a run-up dual-slope circuit with an input integration time of a whole number of power line cycles.  From there it depends on how much complexity I would accept in the quest for performance but I would see how far a simple design can be taken with automatic calibration and precision linear parts before duplicated what HP did.

[Kleinstein]

I wonder how those daft bastards at Keysight got it working with a C0G cap though. But the main performance increase actually came from improving the comparator, its what made the multi-slope conversion feasible.

Some C0G/NP0 capacitors are pretty good as I discovered designing sample and holds.  I was surprised when I ran across old run-up dual-slope converter designs which used silver mica capacitors.  After that, I wondered why anybody was using dual-slope converters with picky capacitors at all.  Maybe nobody could understand how the run-up dual-slope converters worked because application notes from Siliconix were so poor; I am not convinced now that even they understood them.

C0G/NPO caps can be pretty good - about the quality of high quality film caps (e.g. PP or polystyrene), but much easier to solder in SMT. So they are an obvious choice today, if you don't need a very large cap, like in the slow dual slope designs (e.g. ICL7106).  In an dual slope converter DA of the cap will cause some INL and gain error (as DA can be temperature dependent this would include some drift). To a lesser extent in a multi-slope converter DA can also cause some INL errors - though considerably less as normally the cap is much smaller and the mean voltage at the cap is small.  My guess is that much of the INL of the ADCMT 7480T (see parallel thread)  and similar 6581 is due to DA in the rather large integration cap.

The plan shown by Mickle T. looks nice - like a more modern and improved version of the solartron design. I am just a little surprised it used extra HW counters instead of the input capture function of the µC - this could have simplified the digital HW a bit.  It is definitely a way to get high resolution, good INL with a moderate effort.

[David Hess]

To a lesser extent in a multi-slope converter DA can also cause some INL errors - though considerably less as normally the cap is much smaller and the mean voltage at the cap is small.  My guess is that much of the INL of the ADCMT 7480T (see parallel thread)  and similar 6581 is due to DA in the rather large integration cap.

The run-up dual-slope converter drives a lot more charge through the capacitor making it seem much larger than it really is.  So the error from dielectric absorption is distributed over a much larger amount of charge producing a smaller error.  Offsetting this is charge injection from all of the extra switching but if balanced out, then this produces an offset error which is calibrated out.

The plan shown by Mickle T. looks nice - like a more modern and improved version of the solartron design. I am just a little surprised it used extra HW counters instead of the input capture function of the µC - this could have simplified the digital HW a bit.  It is definitely a way to get high resolution, good INL with a moderate effort.

I would have to do the math to be sure but an external synchronizer might be necessary to limit measurement error due to jitter.

[Kleinstein]

The plan shown by Mickle T. looks nice - like a more modern and improved version of the solartron design. I am just a little surprised it used extra HW counters instead of the input capture function of the µC - this could have simplified the digital HW a bit.  It is definitely a way to get high resolution, good INL with a moderate effort.

I would have to do the math to be sure but an external synchronizer might be necessary to limit measurement error due to jitter.

There is a synchronizer (e.g. the 2 flip-flops U30A/B) behind the comparator.  Behind that it is in sync with the µC clock and could thus be sampled with the µc's ICP function, with no more extra jitter. One just needs to be sure the phase of the clock is not just at the wrong point.

For jitter reasons I would prefer a canned oscillator.

Besides the modernization of the HW, there could also be the option to modify the software side a little. AFAIK the solartron uses only sampling at the start and end of the integration time. With a little more processing power it is possible to look at a few more transitions at the beginning an end. Averaging could reduce noise a little, at the cost of a small change in frequency response (might even be better this way) and only slightly increased time (e.g. a few periods of the forcing signal). With averaging it might be attractive to use a slightly faster forcing signal.

The full ADC with a +-xx V range would need a FB from the positive reference too and will get quite sensitive to the ref. inversion (R4/R5). The solartron uses a very higher quality resistor at this position for a good reason. A capacitive ref. inversion might be an alternative.

[David Hess]

The plan shown by Mickle T. looks nice - like a more modern and improved version of the solartron design. I am just a little surprised it used extra HW counters instead of the input capture function of the µC - this could have simplified the digital HW a bit.  It is definitely a way to get high resolution, good INL with a moderate effort.

I would have to do the math to be sure but an external synchronizer might be necessary to limit measurement error due to jitter.

There is a synchronizer (e.g. the 2 flip-flops U30A/B) behind the comparator.  Behind that it is in sync with the µC clock and could thus be sampled with the µc's ICP function, with no more extra jitter. One just needs to be sure the phase of the clock is not just at the wrong point.

I am just pointing out why I might not rely on only the input capture function of the microcontroller or an FPGA for that matter.

For jitter reasons I would prefer a canned oscillator.

I would prefer a discrete oscillator.

The full ADC with a +-xx V range would need a FB from the positive reference too and will get quite sensitive to the ref. inversion (R4/R5). The solartron uses a very higher quality resistor at this position for a good reason. A capacitive ref. inversion might be an alternative.

I have been considering whether capacitive multiplication and division might also be good for linearity calibration.  Don't some of the Keithley meters do this?

[Theboel]

@ David Heiss
I would prefer a discrete oscillator.

could you more detail about this
Thank You
Anton

[Kleinstein]

Some meters use capacitive multiplication / dividers. I know of the Datron 1281, the Keithley 2002 (but not sure if used for ohms only) and a kind of odd way in the K2001. The reference part of the K2001 deserves a few  .

The main advantage of the charge pump type divider it that it is stable, but it does not give an absolute accurate 1:2 division due to parasitic capacitance and charge injection. So it can can not be used for INL cal by assuming it will produce exactly half or twice the voltage. However it could be a good solution to get a precise negative reference for the ADC. The other possible use would be to get a long time stable 1.75 V (7 V / 4)  to do an gain adjustment for a 2 V range.

For the integrating ADC with charge balancing, the negative reference needs to be precise, as drift in the reference would transfer to DC drift and gain drift. However it is usually possible to do a measurement for adjustment of the absolute value so that the negative reference does not need to be accurate or long term stable. So the charge pump type inversion would be definitely an option. This is especially true for the type of ADC Mickle showed, that is slow in doing an offset drift compensation.

[David Hess]

@ David Heiss
I would prefer a discrete oscillator.

could you more detail about this

I mean for reliability, cost, and performance reasons, I would rather use a discrete transistor crystal oscillator than a hybrid or integrated oscillator unless the application is not critical or the cost is not important.

[Kleinstein]

A discrete transistor crystal oscillator might get better ultimate performance, if made right and well shielded. However the canned crystal oscillators are relatively cheap (e.g. $1-2 range) and already shielded and seem to be sufficient - many DMMs use just such oscillators.

An important point can be a good supply decoupling with the oscillator, as the oscillator could react to supply variations and also can be a significant source for RF emissions. So an extra ferrite in the supply line is likely a good idea.