Advantest R6581 8.5 digit DMM mini teardown/repair

[Kleinstein]

The 1 V range turn over test shows quite some scattering, kind of like expected. So it is hard to tell if it is really better - 1 µV in the 1 v range corresponds to 10 µV in the 10 V range if the error comes from the ADC.

On thing one can see from this, is that the problem is likely not from the input side of the amplifier. So U108 or similar, as here the 1 V range is really better. This also includes the input side of the amplifier. But it is still impossible to tell if the problem is more like the output side of the amplifier or the ADC.

One possible source of nonlinearity is an effect of the input voltage on the reference voltages (+17V and -19V). This could happen from a not so good layout of the ground path, e.g. like input dependent current flowing through a ground path also used for the 7 to 17 V step. However this would cause a kind of square law contribution over the full range, thus no saturation of the error in the 1-6 V range like observed. In addition this type off error would effect essentially all instrument of one board revision in a similar way (unless the current is due to non perfect compensation).  I am not sure the 34401 is sensitive enough to see a possible effect of the input on the +17 or -19 V reference. The problem is that this would need the 100 V range and would thus likely be not easy to measure. One should however be able to see individual ground points shifting - however here the problem is of deciding where to have the real ground.

I don't really expect this kind of beginners mistake in the circuit - but one never knows. Sometime even simple mistakes happen in higher grade instruments.  This meter (and some others too) has some really odd design choices that makes me think  .

A different timing in 100 PLC mode realized as 10x10 PLC and the normal 10 PLC mode is kind of odd. There might be the try to make the 100 PLC mode to use 100 x 20 ms for sampling the input, 100 x 20 ms for sampling zero and also make the total time lost to rundown and reset also an exact multiple of 20 ms (e.g. 20 ms,40 ms or maybe 60 ms). This could reduce the effect of 50 Hz residue a little, as than the starting phases would be evenly spaced. It could be just two separate parts of code independently written / modified and with no deeper thought.

[TiN]

Kleinstein

I am not sure the 34401 is sensitive enough to see a possible effect of the input on the +17 or -19 V reference. The problem is that this would need the 100 V range and would thus likely be not easy to measure. One should however be able to see individual ground points shifting - however here the problem is of deciding where to have the real ground.

I can measure using two 2002's, which have 20V base DCV range, if someone guide me thru setup and points to measure.

A different timing in 100 PLC mode realized as 10x10 PLC

3458A does same thing, AFAIK.

[szszjdb]

Hi,  Mr. Mickle.T and Mr.Kleinstein ,
I had checked the turn over test in 1v range again, attached FYI. It seems a liitle different comparing to the last record.

I have installed the new gpib-usb cable and is learning to use.

EDIT: I found I can read data back from 6581 and 34401 in KEYSIGHT IO , but have no tools  to record it.  Is there any software can do the job? I am using the AGILENT 82357B , GPIB-USB cable.

I got a 6871, which is 20V range right for the 19V/17V test and will try it tonight.

EDIT: I had checked the 17v/19v/10v with 6871 and  the reading are 16.695942v/-18.659821v/-9.821943v. It have nearly no change with input switch from 1V to 10V.

Best Regards,
szszjdb

[Kleinstein]

The turn over error in the 1 V range looks quite different from the old data and also different from the 10 V range. However this must not say the error observed in the 10 V range must come from the amplifier. There can be be some compensation of errors in the 1 V range. The prime candidate for the is resistor self heating, though this would be a contribution proportional to u³ and thus not visible in turn over tests. especially the higher voltage end looks better at 1 V.  I am afraid the 1 V range turn over data are just to uncertain to really get much information from this.

For recording data and controlling the meter quite a few use Python scrips. A first point to check with the PC interface could be input leakage over a larger range by looking at capacitor (e.g. 1 nF PP/NP0) charging from input bias.
 
The relevant reference points for the "17 V / 19 V" would be something close to the current sources. Thus maybe the outer ends (17/19V) of R200 and the +-2 V levels of R201. Instead of the +-2 V level the center ground near R201 should be nearly as good. This should be rather close to the input of the current sources.  A problem could be getting the probes there without disturbing the resistors too much.
 

[szszjdb]

Hi,  Mr. Mickle.T and Mr.Kleinstein ,

Thanks for all!

I will re-check the +17v/-19v around R200 this night. I was test them on the u209/210 ,where found no change when switching from 1V to 10v.

I found some uncertainty with my resistor string , so replaced the switch. Then I measure the 6581 INL by the method again compared to my 6871 for twice. The data is attached FYI.  It is clear that:
1. both test can repeatable and the negative INL is much better than the positive one.
2. The odd is the 6871 is more like the 6581 in the positive INL, although they are the same kind of design, there still have detail in different.
3. My INL curve is more like the one made by Mr. Mickle.T.  I also attach them ,FYI.

Would like to have your advice.

Best Regards,
szszjdb

[Kleinstein]

There should be a way to connect the INL test for the positive and negative side to one curve. They are measured separately, but the curve should continue to the other side, not just connecting the INL data, but also doing the linear fit over both sides.

I have the suspicion that up to about 6 V the positive side may be OP and just above about 6-8 v something happens, making the curve turn down hard.

Having a rather similar curve with the 6871 meter could be a general weakness of the design - again not clear if this it the amplifier or the ADC.
I don't see anything special at around +8 V. It is too low to expect beginning saturation at the input amplifier. The positive end is where the gate - drain voltage for the MUX JFETs is largest. So it might be something like starting leakage at the input.
The relatively strong downward trend at large positive voltage might be strong enough to see the corresponding effect in the 1 V range too. As the turn over error stayed low in the 1 V range point's away from the ADC. 

[TiN]

Would the simultaneous measurement of Vin at 6581T input AND at the 6581T AD IN node give more insight on this matter, to determine where error come from? I can use two 3458s for that.

[eurofox]

I joint the club, I have a R6581T coming to my lab soon.

It is supposed to have a battery issue but we will see when it is here. 

[Kleinstein]

Would the simultaneous measurement of Vin at 6581T input AND at the 6581T AD IN node give more insight on this matter, to determine where error come from? I can use two 3458s for that.

Measuring ADin together with the output of the 6581T  is not that simple: without AZ mode there can be quite some drift that would make an INL test difficult to impossible. To get a good chance it would need a controlled input waveform with a few repeats (because of 1/f noise of the 6581). In the AZ mode there would be alternating signal and zero. So it would need something like a triggered measurement and there is a chance to get additional error from settling if the measured time in different. It might work from recorded readings at 1 PLC and sort out the data afterwards.

Similar a good measurement of the difference from input to ADin could give a test for the amplifier. No need for higher resolution here, more like a µV measurement calling for very good common mode suppression. But again one would need some suitable input waveform to do the test and drift and 1/f noise makes the test tricky. So it would be more than just connecting the meter. One might have a chance to directly see the error with an AC test: Apply a low frequency (e.g. 1-10 Hz ) AC to the input and do synchronous sampling, (looking for harmonics) of the difference over the amplifier.

[szszjdb]

Hi,  Mr.Kleinstein ,

Many Thanks!

You means the INL might causing by the leakage of input amplifier or MUX? But how to explain the data measured from HI port to ADIN? It seems ok from that picture.

I will check the INL in 1v range to confirm it.

The INL curve is perfect in 6581's datasheet and bad in my and some similar case. There must have some parts failed.

EDIT: I had test the INL for 1V range. It seems like the 10V range in the curve. So can we  say the issues MUST be in the ADC?

Best Regards,
szszjdb

[Kleinstein]

The input to ADin curve is not a perfect line. This could be due to noise, drift or similar, but if real it reflects some INL error.
If one assumes the slope of initial part of the positive side, this could be an error in the 5µV range at the + or - 10 V level. This is less than the observed error in the INL test, but still more than specs. The observed deviations from a straight line could however be very well just an effect of amplifier drift and LF noise. The real measurements will correct for this in the AZ mode.

Extra leakage could be due to aged or defect (e.g. ESD damage causing more leakage) parts, but also due to contamination of the board. There can be states in between good and definitely broken.

If the INL test in the 1 V range looks like the 10 V range, this points towards the ADC. It more or less excludes the input side of the amplifier and the MUX, but in theory it could still be the output side of the amplifier. I don't see much at the output side of the amplifier to cause that type of problem, so it is very likely the ADC itself that causes the INL error.

I am kind of curious how the voltage at the output of U205 and U202 looks like. I would expect a kind of rectangular waveform with moderately slow (e.g. 1-5µs) slopes/ settling. Too slow a response at U205 could cause some INL.  Form simulations I did on a similar integrator the resistor value for R216 looks relatively high to me and this could cause a relatively slow response. For the output of U203 there can be some ringing / peaks when switching. How much depends on the switching of Q204/Q205 and symmetry of Q204/Q205. A comparison between a good and bad meter might help here.

In the schematics it is a little odd the substrate pins are not connected. I would expect a connection to ground here.

C207 looks like a ceramic cap. Some higher value MLCCs show aging. I don't think the value is that critical, but at the PPM level there are many possible effects.

[Mickle T.]

All substrate pins are connected to -3.3V (U204/2 op-amp driver). I think C201, C204, C207 are film SMD capacitors, not MLCC.

[szszjdb]

Hi,  Mr.Kleinstein and  Mr. Mickle.T ,

Thanks a lot.

I will test the waveform tonight.

EDIT: The waveform for U202/U200 pin6 is just an DC voltage. And for U205 is near zero signal. For U206 is a sawtooth wave.  The cap on the ADC were CL type.

Would like to have your further advice?

Best Regards,
szszjdb

[Kleinstein]

For U202 chances are that there is very little AC part. This indicates that Q201 already makes a pretty good current source and/or Q204/Q205 are well matched. So it is not such a big surprise to have very little signal.

The signal from U205 looks quite noisy. If this is not just a problem of the scope or probe, this could point to no so good decoupling.  The signal is small as expected,though a little less than I had expected. Because of the noise / higher frequency background it is hard to detect the time it takes for settling after the jumps - it is already hard to see the jumps.  The interesting part is about 40 to 60 µs after the marker, but I am afraid one would not see much more with a zoom in anyway, even with filtering. At least no really slow settling visible - the decay back to zero over around 20-50 µs should be just the capacitor charging. So C207 should be at around 20-50 nF.

The higher frequency noise might be worth looking at a little more. With so much high frequency crap, all kinds of odd things can happen.
I am afraid the substrate "B" signal to the FET switches will not look clean too. Such a more continuous background could come from something further away, like the crystal clock, the µC or similar.

The Output of U206 is the integrator output and thus the expected triangle.

[szszjdb]

Hi,  Mr.Kleinstein  ,

Thanks a lot!

I will make more pricision test with my scope tonight.

Further question about the 10v range INL, although the negative one looks better in ppm scale(<0.2ppm), it is still very large(15uv each)  error between the V source and the V measure in the uv scale. The V source is the sum of the single resistor voltage ,which is measured both in 10v range.
What might be the  reson for it?   Attached the curve , FYI. Also attached the scheme of my KV divider.

Best Regards,
szszjdb

[Kleinstein]

One reason for a relative large error for the direct difference can be the error from the 10 to 1 V range transfer.
Another possible error source could be an offset error that adds up with the steps. The linear fit can to a large fraction compensate for this.

A big problem can be drift of the references during the measurement. This can look like a nonlinear part. For the reason it might be needed to do a repeated measurement and not just a single measurement each.  A set of measurements would be something like:
1) the single resistor voltages
2) the sums (e.g. 1 , 2, 3, ...10 V and -1, -2 ....)
3) the single resistor voltages again to check for drift and get an idea on how much drift is expected.

Another possible problem can be input current - this would show the most effect in the center of the resistor string and could this way explain a curvature as observed for the positive side.

It is a little odd that the single resistor voltages don't match for the positive and negative side. They are quite different and might indicate drift.
 Also the first voltage should fit rather well.

[szszjdb]

Hi,  Mr.Kleinstein  ,

Thanks a lot!

I measure both the voltage of single resistor and the sum of it  in 10v range, so the error  might come from the INL itself?
The offset of each range is near zero. Where is the offset come from?

The drift of the voltage has the max 1-2uv recorded and it might come from the banana socket . It 's a repeatable test and I was doing them exactly like the step you mentioned.

The input bias is about 0.2mv on an 9.7M resistor.
The turnover test shows the different between each.

I went to my friend and recorded the performance of his 3458. All the test platform is like in the 6581 test. As attached , the INL is nearly <0.2ppm ,and the sum of the resistor voltage is near the measured.

I will test the waveform tomorow night.

Best Regards,
szszjdb

[Mickle T.]

R6581T INL in the full +-10V range   
Measured with Datron 4000A (0...+19.999999V with 0.1 ppm INL) and subtracted 10 V from LTZ1000 vref.

[Kleinstein]

The idea of the test with the resistor chain is to measure INL at a few points. As ideally INL is rather small, one usually has to push it hard to avoid other errors. Offsets in the 1-2 µV range, e.g. from hand warm banana plugs might already be a problem.

A second type of difficulty can be settling of the meter and reference drift. A fast measurement sequence might see settling effects, while a slow sequence would see more drift effects. One could do a separate settling test with sending the data to the PC.

The different values (1.3 µV) already at 1 V and thus only the first resistor kind of indicates a problem - either with drift or quite a lot of offset. How good do the measurements of the resistor voltages match initial and at the end ?
One should be able to have both the positive and negative side in one curve (with 0 in the middle) - the voltages over the single resistors can be measured with one sign and than give a continuous sequence through 0.


With the PC interface one should be able to check for input bias at a few more voltages (e.g. with the drift seem with a good quality (PS or PP) capacitor in the 1 nF range). Alternatively one could do the test with and without an extra series resistor.  Even if the input bias is in specs (e.g. < 100 pA), one might have to apply corrections, as the source impedance changes with the resistor chain. 

As the meter does not use a pre-charge phase, there is a chance that there is some "charge injection" from the MUX changing between 0 and input. If this changes with voltage (which is to be expected) and input impedance this could cause some extra errors. It might be worth doing a test with a positive voltage (e.g. 5 V, 7 V or similar), comparing a few different series resistors (e.g.  0 Ohms,  100 K , 1 M) - if there is a significant difference, this would indicate an input related problem. Capacitance at the input (e.g. C008) could make a difference too, as the switching includes dynamic effects. There is some chance that switching can be different when going up or down in voltage so this could cause a difference between positive and negative voltages.
One might be able to see switching artifacts with the scope at the input.

[szszjdb]

Hi,  Mr.Kleinstein and  Mr. Mickle.T ,

Thanks a lot!

The main drift might came from the EMF of the banana jack and the switch of the divider. But it is almost in the 1-2uv range and can be considered as the system error of my test platform.  I will change the banana jack to low EMF type later.

I also noticed some more noise coming when testing the 3458 in the 6-8V input from the string resistor. The digit of uv jump more than the other voltage like 1-2v. I don't know the reason.

Would you give some detail advice on the PLC and interal setting when check the bias with the capacitor ? I can read back data from GPIB port now.

I just repalced back  the r200 to the original one ,so will do more test tomorow night.

I also comfirmed that all my early test are conducted under the PROTECT on mode, which connected the C008. I will  test again under PROTECT off mode.

Best Regards,
szszjdb

[Kleinstein]

The noise in the center part of the resistor string can be higher for two reasons:
The first is just Johnson resistor noise. With a 10 K string in the center output resistance is up to 50 K and thus noise of up to about 30 nV/Sqrt(Hz). I don't think one would really notice this in the 10 V range. In addition there can be some low frequency excess noise - though I doubt it will be much with only about 1 V per resistor.
The DMM input will have some current noise, not just voltage noise. There are rarely specs for this, but it can be quite a bit. Especially for the 6581 this can be relatively high from the way the JFETs are switched in the AZ mode.

At higher voltages there is additional noise from the references (both the meter and external source).

For checking the drift with a capacitor one could test the 1 PLC and 10 PLC mode. The 1 PLC mode would have a higher switching frequency and thus more contribution from charge injection. With a 1 nF capacitor the drift would be around 10 pA/1 nF = 10 mV/s . This does not need the high resolution of the 100 PLC mode. One could even check the non AZ mode for comparison. So the test would be to save the data to a file, have the cap at the input and than apply a voltage of the points to test (e.g. 1,2,3,...10 V) for a little while (to allow DA of the capacitor to settle) and than get the actual drift reading for maybe 10 seconds. Alternatively one could start at 10 V / 0 V/ -10 V and use the drift to cover a larger voltage range. At 10 mV/s this might take some 40 minutes to cover the full range. A slightly larger cap might help to reduce the effect of the internal cap to get more accurate absolute values.

Ideally the voltage reading should not change between the protect on and off mode. One could check that, especially with a voltage source that has some output resistance (e.g 100K-1M range). There will be some settling (e.g. 300 pF*100 K = 30 µs , thus short) but ideally no other change. I would not expect much DA effect form the capacitor - though it is odd to have a MKS type here. I would have expected a low loss type like NP0 or MKP.  However charge injection could be influenced by the capacitor and something like a change in the input current of a few pA would be visible. With a 5 Hz switching frequency this would correspond to a change in charge injection in the pC range. I don't know data on JFET switching, but I would expect about that order of magnitude - maybe considerable more if the limited slew rate of the OP07 (U107) comes into play. So there is a possible effect.

[szszjdb]

Hi,  Mr.Kleinstein and  Mr. Mickle.T ,

Thanks a lot!
I tested the noise of the LTZ1000 ref. PCB with AZON and AZOFF mode. Attached FYI.
I also checked the bias voltage on the 1nf cap with or with AZ and attached.
All the  test  was  on 20 PLC .

Best Regards,
szszjdb

[Kleinstein]

The noise test at 7 V looks good. There are a few out-layers. The lower noise level in AZ mode is normal due to the 1/f noise of the amplifier that is suppressed by AZ. 

The test with the capacitor shows very little input current: the negative side shown a slope of around 3 mV/s which would be a current of only 3 pA with a 1 nF capacitor. Due to internal capacitance real current is a little higher (maybe 50%).

The test with AZ and positive voltage shows a voltage / time dependent drift. Starting at around 10 mV/s this would be about 10 pA but leveling of.
A change over 100 mV corresponds to a 10 GOhms differential resistance.  This might cause some trouble with higher impedance signal sources.
So it would be really worth doing the similar test at different voltages, to gets input current over the full -10 to 10 V range.

[szszjdb]

Hi,  Mr.Kleinstein and  Mr. Mickle.T ,

Thanks a lot!

Would you please give me some advice on the detail to add the voltage  with the cap.  Parellel the cap with the HI/LO port,feed the input  with a voltage source setting at 1V, and then plug out the feed line?

I had buy the new  U401 for Q102 and am going to replace it to fix the INL of the DC amplifier(about 5uv ). Can I do it ?

Best Regards,
szszjdb

[Kleinstein]

...
Would you please give me some advice on the detail to add the voltage  with the cap.  Parellel the cap with the HI/LO port,feed the input  with a voltage source setting at 1V, and then plug out the feed line?
......
Best Regards,
szszjdb

This the way I would apply different voltage for the tests. There is no need for exact starting points, it just helps if the whole range in covered. Depending on the input current, one could get away with starting at 10 V or -10 V and than just wait for the capacitor to charge / discharge.

Unless there was another mishap to damage it, I don't expect U401 to be damaged and responsible for INL. If U401 is damages somehow, the first things to expect would be the amplifier to not work at all and maybe excessive low frequency noise. The ref test was OK though.
Subtile INL errors might be from not working Q110, Q107 / Q115 or Q116. However a damage is unlikely. This cold be checked if in doubt.

The one point I find a little odd with the amplifier is the way the guard driver for the JFET input switches is handled. It can take quite some time for U107 to settle ( the OP07 has a rather limited slew rate) and this could cause quite some leakage current through the JFETs, when switching from a positive voltage down. So just for curiosity it might be interesting to look at the amplifiers output and guard with the DMM in AZ mode and with some voltage applied to the input.  Possible problems (and maybe just the normal capacitance / charge injection) when switching would also show up as extra input current - thus the idea of checking the input current at different voltages too.