Advantest R6581 8.5 digit DMM mini teardown/repair

[Kleinstein]

A larger value for C026 will slow down the switching and this way make leakage due to a forward biased gate smaller or less likely. However with to much of a capacitor switching will get too slow at some point. So 1 nF might already be a little to slow and thus cause an offset error. With a larger C26 it might make sense to reduce R083 to keep the turn off phase fast enough.

As the range to increase C026 are limited it makes sense to speed up the amplifier instead of slowing down the switching.

The DCV input switching is slowed down with C026, but other inputs of the mux are still switching fast. This could be a problem when measuring higher resistance like 1 M if measured as 4 wire ohms. The current source is negative side and thus a voltage like -10 V might be present. I don't know if 4 wire ohms is still supported when the voltage goes higher than -5V - it's usually not really needed.

The TL071 is not that much different from an LT1056/LT1055 - so if it works with an TL071 there is no real need to test an LT1056.
Another possible good choice would be the OPA171 due to it's high open loop gain.

[szszjdb]

Hi,  Mr.Kleinstein,

Thanks for all.

I made a mistake that the photo I upload yestoday is PIN27 vs PIN20, not PIN28. The ringin from PIN28 is a little bit small, might due to the gate capacitance load.

Further odd things is that I found the PIN20 have the 100-200mv forward bias to PIN28/PIN7 either in AZOFF or AZON mode. I can confirm that the 2 channel of the scope have the same gain at that point.  It might contribute more leakage from gate to the input channel.  As the PIN20 is pull up by PIN27 by a 100k resistor and the voltage of the PIN27 is exactly the same with PIN28, where is the forward bias coming from ?  Is there any posible the forward bias is design to reduce the Ron of the JFET in the MUX or some part defect?

I am trying the TL071, and report later.

EDIT:
After changing the U104 to TL071, the ringing mostly disappear .  There still has some overshot on the PIN20 for the gate control when with 100p  for C26 and more improvement with 350P.  However the better performance with 350p in waveform testing, there have just a little change for the RIN in the negative discharge test.

The OPA171 is worth to try as the drift of the Vos is 0.3uV/C vs 18uV/C in TL071.  I am just worry about the 3uv Vpp voltage noise, which might degrade the noise performance of the DMM. And further information about the ADCMT 7480 show that they use OP177 instead of  U104 OP07, AD8034 for U105 LT1220 and ad8267 for U107 OP07. Are these the banlance of the noise figure with the speed?


Would like to have your further advice. Thanks!

Best Regards,
szszjdb

[Kleinstein]

There can be a little offset between Pin27 (guard) and the input to the amplifier (pin 28). The gate voltage should more or less follow pin 27 when on.  The offset is mainly due to the offset of the JFETs (Q102) and it should be influenced by the R170 trimmer.  I don't think one should have an intentional offset here and having zero offset could be a good target for adjusting R170. At least Zero offset should give the lowest leakage and it the usual operating point. It's more like a negative offset might be desirable to reduce the leakage due to gate forward bias during transients.


Having pin 20 more positive than pin 27 would be odd, as I don't see many paths to a more positive voltage, Gate leakage should be the other way around.  In theory there could be some leakage in the LM339. This would show as a drop on R083.

The peak at pin 28 after switching looks odd. My guess would be capacitive coupling from the guard to the input. This might be a problem to a faster amplifier, but just the change of U107 should not have changed that much as this step did not give that much speed up.

[szszjdb]

Hi,  Mr.Kleinstein,

Thanks a lot!

Confirmed that the forward bias of the gate is due to the leakage of LM339 and about 1ua current flow to the R83 ,then to the 100K in the MUX . How to fix it ? 

Best Regards,
szszjdb

[Kleinstein]

A quick and dirty fix could be a diode in series with R083. Changing the LM339 would be the natural way.  Another point to look at might be if there is excessive flux residue around the LM339 (normally not that critical and 1 µA is quite a lot for leakage due to flux).

Looking at the newer ADCMT7480 is a good idea. The OP177 is not that much faster than the OP07 - it's main advantage it a higher open loop gain and thus possibly better linearity for the amplifier.  The logical way to solve the switching problem would be to include a pre-charge phase, which is not that difficult and a patent on this should have expired by now. This would eliminate the critical step to towards DCV_in and also reduce the current contribution from just recharging the amplifier input.  I would consider it worth the bit of extra effort.

The crazy way would be adding pre-charge to the 6581: On the rising slope of Pin20 gate add an extra phase that connects the output of U009 first and only than with a delay of a few 10 µs activate Pin20 in exchange to the extra channel.

The noise and drift of U104 should not be that critical: The JFET stage should give a gain of about 20-40 ( S = 1-2 mS for the FETs U401). So drift and noise Of U104 would be attenuated by about this factor. So even the TL071 should not contribute much to the noise and drift.

The way I understand the amplifier, there is little disadvantage, more like an advantage to a slightly faster amplifier for U104. Most JFET based OPs would have the additional advantage that there slew rate would not saturate before the diodes D103 kick in. This would make D103 more effective in limiting overshoot. The step from the U105=LT1220 to the AD8034 might be for a similar reason with D111.
The main downside I see for the TL071 is its lower open loop gain compared to the OP07. I would prefer the OPA171 over an TL071 mainly because of the higher loop gain.

One might have to check the gain of 10 and 100 modes too, if these are still stable. I would expect it, but one never knows.


Edit:
Adding a pre-charge phase might not be that complicated: It needs another JFET path from the output of U009 to the amplifiers input, that is controlled by a delay. A possible way would be an 74HC123 or similar monoflop triggered by the signal to the LM339 that controls pin20 of the MUX. This monoflop controls 2 out of phase drivers (LM393 comparators): one to control the new JFET for the pre-charge path and the other to form a kind of wired AND for pin20.  So for the first around 20-40 µs the pre-charge channel is activated instead of pin20. So it would be a small added board and maybe a reduced value for C026 if the time gets too short.

[szszjdb]

Hi,  Mr.Kleinstein,

Thanks a lot!

The leakage of LM399 is max. 1ua in the datasheet as I measured, that it should be 0.1na in normal.  The U017-1 also contributed to the same forward bias like U016-3 when in the negative reference test. That is to say all the JFET will be forward biased and the more negative it is , the stronger bias it is. That might be the  bug ?
EDIT: The bias can be fixed by just add 1n4148 in serial with R83. It might be the large leakage of the 4148.

After checking the ADIN with the PIN20 in the 1v/100mv range , I found something different with the 10v range. It seems stronger ringing occured in that case.  Attached FYI.

I am going to return the analog PCB back to my friend tomorrow  and I should focus on the INL of the ADC and capture some data for future comparing.  The adding precharge phase is worth trying following.

From the INL testing, I had tested the INL for DC AMP byinput a volatge from resistor string and record the reading from ADIN point at AZOFF mode. It show not so well INL of the DC AMP.  I will test tit on the new analog PCB from my friend for comparing.

Would like to have your furhter advice!

Best Regards,
szszjdb

[Kleinstein]

The leakage from the LM339s could contribute to the leakage. However normally 100 mV more should not be that bad. There are also other parts than can show quite some variations: the JFETs in the mux can show quite some variability in threshold. This could have quite some effect on the point when the switching takes place. Another part with quite some range is the speed of the OP07. The DS I found showed slew rate of only 0.1 V/µs min with 0.3 V/µs typical. I doubt many real world parts would be that slow, but it's quite a range.  They might also do some sample tests not to get a very slow batch.

Using LM339 to drive the JFETs is quite a common practice in DMMs - for some reasons they also fail sometimes, but so far I have not heard of leakage to be a problem with this chip. There are many sources for the LM339 and so there may be good and bad batches / manufacturers. That type of leakage towards positive side is also a quite unusual parameter, that may not be tested so well.

For the relative critical DCV input one could replace R083 with a diode and a smaller resistor (e.g. 1-2 K) in series. This would block positive side leakage from the LM339 here. The other input are likely less critical. A slightly positive voltage at the gate that is active might even compensate some of the usually negative current from the other (usually 6) fets that are off.

There is some visible ringing in the 1 V and 0.1 V range - not really good, but I would consider is still acceptable. The decay is rather slow, bt chances are there is enough waiting time before the measurements starts and the settling of the slow component takes about as long. At least there is a change to get it fixed. The critical point would be if there is a lot of ringing on pin 28 too. Normally this should be considerably smaller, due to the divider / gain.

For the INL test, there might be some noise / drift included. So it might need a few repeats and maybe a few more points to see how much of the error is real INL and what is due to drift / noise. The curve looks surprisingly symmetric (inversion) around 0 - no more big difference in positive an negative side. An important point for these curves could be where to take ground for the 3458. Quite some part of the error could be from input currents. The resistor string has quite some resistance in the middle (50 K) - so 100 pA could already cause a 5 µV error. The symmetric shape may be due to an error in the resistor string, if it is turned around.

For the same setup it would also be interesting to get the data from the ADC in the R6581. The comparison to the 3458 would be a good test for just the ADC. It would be without (digital) AZ, but there is an analog auto-zero for the ADC itself and the amplifier is outside only shifting the test-points. So these data should not suffer much from drift.

Probably the better and more direct test for the amplifier would be to measure the voltage between the input and ADIn testpoint (= com of the second meter).

[szszjdb]

Hi,  Mr.Kleinstein,

Thanks a lot!

I had tried the 1N4148 in series with 10k and just a little improvment to the forward bias. I will find some new LM339 for testing.
The INL from ADIN to INPUT  HI seems better than before. Attached FYI.

Best Regards,
szszjdb

[Kleinstein]

The INL of the amplifier would be the deviation from a straight line of that last data. Just by eye (which is usually quite good in guessing a straight line fit) there still seem to be errors up to maybe 3 µV.  So it is not that good. Normally I would expect something like less than 1 µV deviation, for much of the range even below 0.1 µV  (if scattering and drift are removed).

However this test also includes amplifier drift. So it would need quite some repeats (e.g. going up / down 2 or 3 times, ideally more)  to get some averaging in the drift / scattering and an idea on how reproducible the points are. So a really stringent linearity test of the amplifier would likely need an automated setup that could run many repeats at a constant rate so that drift and noise could be averaged out.

The amplifier (at gain 1) is the easier part compared to the ADC, when it comes to INL. The main uncertainty might be input current in combination with the 8.8 K resistor at the input.

What about is the level of input bias current reached by now ?

[szszjdb]

Hi,  Mr.Kleinstein,

Thanks a lot!

The bias reached around 1.4na and the RIN is about 5-6Gohm arround 8v voltage. Attached FYI.

Futher testing with the INL oF the  DC AMP shows that the MAX. Err of the amplifier is below 1.5uv. It seems acceptable. I am using the 3458 in 200plc to get the reading ,which is stable enough.

I have assemblyed back the new analog PCB and will check the control gate with the scope.

EDIT:
The  INL reading of the DC AMP is not so stable ,likely more noise coming in the new analog PCB, so drop it. It is hard to record the data from the DC AMP. duo to the drift and noise. Howere, the INL is not so bad from the data I had got. The main INL issue is duo to the ADC itself I think.

Would like to have your advice!

Best Regards,
szszjdb

[Kleinstein]

It is quite natural to see quite a lot of drift / low frequency noise when measuring the difference over the amplifier (input Hi to ADC_in). Most of this would be low frequency noise and drift from the amplifier, especially Q102 (U401).  How much drift can depend of the unit, as not all FET pairs are the same.  To get a good reading here it would take the average over many runs and thus normally some automation. High PLC setting on the meter could be even negative, as it makes the measurement slower and thus more drift.

I agree that most of the INL is very likely from the ADC itself.  A comparison to the 3458 could be relatively easy with a comparison from reading at AD_in and the r6581 reading. Here there should be no extra drift despite of measuring without AZ, because there still is a kind of analog auto-zero for the ADC itself. So the reading should be quite reliable (if done at the same time). However it would not include effects due to switching for the AZ mode - here DA could have an effect though to a large part linear.

However there could be still some contribution from the input current: 1 nA and the 8.8 K at the input already gives 8.8 µV of error.  The input current is not just described by a constant input resistance, but nonlinear (considerably higher current at 8 V than at 4 V). With the amplifier I see the problem more with input current than with nonlinearity of the amplifier (at gain 1) itself. However the input current is not a continuous current but in peaks. So the measured average current is not what is relevant to overall INL when doing a test with a low impedance source. The peaks during switching tend to be less relevant to the measurements on a low impedance source, a high impedance (and possibly capacitive) source will smear out the peaks.

Even the TL071 should lead to very good linearity for the amplifier: The loop gain would be about 20-40 for the FET stage and 33 for the final stage in addition to U104 (e.g. about 100 V/mV with 1 K load for the TL071). This would suggest INL in the 0.01 ppm region.

[szszjdb]

Hi,  Mr.Kleinstein,

Thanks a lot!

I had test the Vadin with 3458 vs  the reading of 6581 in AZOFF mode at 100PLC. However it still  has some drift/noise , the error of record by hand should be less than 1uv  . Comparing to the INL result , there might have the same trend in the two curve.  It is clear that the bad INL or the turn over error are due to the same reason , that some parts might degraded in the ADC.

What might be the reason?

Would like to have your further guide!

Best Regards,
szszjdb

[Kleinstein]

The general shape of the 6581 (ADin) vs 3458 curve looks kind of plausible. The really odd point however is the drop at around zero. Without the drop the main part is parabola as the lowest order of possible nonlinearity. I still don't know what could be the source. It kind of looks two types of error: one is the more or less smooth parabola and the other type an error rather localized around zero.
For that drop around zero it might be interesting to get a few more points, as to estimate on how large the range is that is effected.
For a wrong reading just for a very small range there could be a kind of coupling effect at a special PWM ratio for the feedback. So this would be a very narrow range (like may +- 1 mV) around zero that is effected. However older tests suggested the effected range is wider, more like 0-1 V.

The test with reading at ADin might be effected from 2 drift parts. One would be the amplifier in combination of not reading the 3458 and 6581 at the same time (especially by hand). If reading at the same time amplifier drift would be just like the test source slowly moving and thus not a problem.  Another drift contribution would be from the resistors (e.g. R200) and -19/17 reference ratio.
Still I think this test would be the best way we have to check the ADC, especially if this could be run in a kind of automated way (read 3458 and 6581 via GPIB and maybe also control a source (no need to be stable/accurate, but low noise would help).

Much of the turn over error near zero points towards a problem with the zero reading maybe caused by that odd drop around zero. Still there is something going on between 3 and 4 V.
Somehow the turn over test and the test at ADIN don't really match up. In theory one could calculate turn over errors from the ADin test and those values don't seem to fit. So there might be an extra contribution in the turn over test, maybe due to input current.  The other difference is using the non AZ mode versus the AZ mode.

Ground shift could also be a source of INL. I don't see a good star ground, but it looks a little like a partial ground plane - which is usually not such a good idea with a high precision circuit. With a sensitive meter one could check if and how much the different ground points move relative to each other, when the input voltage changes.  This would likely be just a small change of a few µV, maybe 10s of µV, but the 3458 should be good enough for this.

One point that makes me slightly suspicious is that there are several points where the shield on the back / case is connected to the board. Are these point's on the board electrical connected or is there just one of the screws with a contact and the other isolated on the board ?

One type of INL I would expect is due to self heating of the input resistor inside R200 and this should be more like a 3rd power contribution. However this type of error is not visible. So it looks like R200 is really good quality. The heating due to input current and that way changing the 10 K or 20 K resistor value could give a contribution in parabola form.  Though originally centered around -2 V and not around 0 V, the linear fit brings it to the center. so the shift would not be noticed. Still it would be odd to have a very good 20 K resistor (center part of R200) and than a bad 10 K or 20 K resistor in the same case.

[szszjdb]

Hi,  Mr.Kleinstein ,

Thanks a lot!

The analog PCB have just one point connected to the groud plane ,which is the red marked screw. The green screw marked is my test ground for connect to LO port of 3458. Attached FYI.

I will find a GPIB cable to connect the 2 DMM to read them in the same time. However, I am quite sure that I manually read them at once and the error should be but not so big.

For the R200, I have change them to 4 pcs 20k (2 in parallel and 2 in serial )VISHAY S102C metal foil type resistor before and find no obvious change on the INL or the turnover error in the short term view. Some my fiend have ordered the custom vhp type from VISHAY  and will get on July. Maybe I can get one to try at  that time.
For the resistor of using in -19/+17 generating, I have added some sponge around them to protect the air flow direct on them and the total drift of the reading will be 2-3uv for whole night in AZON mode when testing my LTZ7V reference.

I also noticed that the different of the reading between the AZON and AZOFF mode somtime would be more like 6-7uv and some would be 2-3uv. Is that normal?

Any further test should I make?

EDIT:
I remember that Mr.Mickle T. have found a way to fix the INL by shift the zero ponit by a resistor connecting to +27V.What might be the reason for it ? I will also try it.

Best Regards,
szszjdb

[Kleinstein]

Having only one ground connection is good - this is how it should be.

I would not change R200 again. The resistor seems to be quite good quality, as there is essentially no U³ part in the INL visible. So I would expect it to have a TC in the < 1 ppm/K range. So better handle it with care. It may not look like a very special part, but it seems to be of really high quality.  If at all one could do a test if the TC matching of the outer two parts is good:  In the non AZ mode the effect of a temperature change of R200 on the offset would reveal the TC matching. A slight temperature change could be from a flow of warm air (e.g. 50 C) or maybe a small heater near by. The 2 resistors effectively work like a divider 1:1 from +-15 V. So 1 ppm of change would result in about 15 µV for the reading in 10 V range. So the test could be reasonable sensitive to see even TC mismatch in the 0.1 ppm/K range. Because of this rather high sensitivity good resistors are required here to make the non AZ mode work well.

Ideally there should be essentially no offset between the AZ and non AZ mode, as the non AZ mode should use the last available AZ reading to get it's zero. Over time there might be some drift in the non AZ mode of cause. Due to DA there might be a kind of error, as the zero reading could (is expected to)  depend on the applied voltage before. There is a chance the AZ mode will have a slightly lower gain. As this effect is expected, there might be some numerical correction for this - and in this case the difference could be both directions. The correction is difficult, as the  DA effect can depend on temperature - not just a little but possibly a lot (e.g. up to doubling for 5-10 K more, as many DA effects are thermally activated and faster acting DA would have more effect).

Though not directly connected to INL one could test this, by comparing the AZ and non AZ mode readings at a few voltages (e.g. 0, +-4V, +-7V). As there can be some random / noise contribution it might need a few cycles (like 3 or 4 times switching between Az and non AZ for a few 30 seconds each). At can take some time (e.g. 10 seconds range) to adapt to the new mode / voltage. This very slow settling part could be seen as INL in some tests.

The AZ mode should not show a significant drift over time - so more like a few 100 nV, a 2-3µV drift in AZ mode is kind of odd and would indicate a problem, more like with the MUX/switching or maybe input current related, not the ADC itself. The wrong relay control could contribute to this - so if not done it would be time to fix that. Some drift over a few minutes just after measuring a higher voltage might be due DA effects described above. So the history before such tests might be important.

Shifting the ADC range could be worth a try. Though I would not use the +27 V, but more like the +17 V of -19 V.
I see 2 possible reasons why the shift could help: one would be that the +27 V is slightly changing and this way compensating the non-linearity.

The 2 nd way would be that the zero reading is just a bad spot for the ADC and thus using this bad spot causes trouble. There is a chance that some value near zero can be bad, as for a rather small range (e.g. something like 1-10 mV, maybe less) there can be capacitive coupling from a clock that has a transition just before the feedback-current switches during run-up. So a rather small range of values could give rather large errors and if these are just used for AZ this may not be so good. The shift could just move that tiny bad range away from zero,  if it just happens to be at zero. The trimmer at the DC-amplifier could have a similar effect - so I would not expect too much of an effect.

[szszjdb]

Hi,  Mr.Kleinstein ,

Thanks a lot!

The big difference between the AZ and non AZ mode is mostly occured when switching from non AZ to AZ mode. I will make more test as your guide.

The long term drift (2-3uv/day)might causing by the sordering effect of the R200 or some other parts recently modified.  That  could be corrected by re-doing the internal calibration and seems have no effect on the INL or the turnover performance.

For the shift the zero point of the ADC , I noticed the current added by Mr.Mickle T is about 30uA, equivalent to 0.5V zero bias. That might have huge influence  to ADC . But I am wondering how it can get the right reading without the ACAL.

I remembered that you have metion the +5v power supply for U208 might have issue. How about adding a second +5v regulator like 78l05 instead of just a zenar? That might reduce the nosie in the comparator.

EDIT:
Here is the drift between the NON AZ vs AZ mode. Normally the NON AZ mode will have larger number. When back from AZ to NON AZ mode , the reading will recover slowly.

Best Regards,
szszjdb

[Kleinstein]

The soldering on R200 should not effect zero drift in AZ mode. If would be only the non AZ mode drift that can be influenced, but this is usually not that critical and still good. For the drift in AZ mode I would more like suspect the input relay (especially if still running hot) and maybe still some effect from input current / switching. If for some reason the input current drifts this can add to input offset. However switching at zero input voltage should be about the best case and thus not problem with gate bias or similar.


For the offset added, it might not take that much to have in influence on the INL (e.g. if the poor range is small). So it might be possible to stay in the range accepted by the self test. Depending on where the offset is added, it should not have a significant effect on gain. So it might be still possible to do the self-test and maybe even ACAL without the offset and only than enable an offset. Anyway I would not consider this a solution, more like a hint that might help to find the problem.

The usual 5.6 V zener is lower noise than an 78L05. So I don'T think this would be an improvement.

I had expected a slightly larger difference between the AZ and non AZ mode. So the capacitor seems to be low DA. As the ACAL measurements are done in a kind of AZ mode, I would consider the AZ case more accurate - though it is only in the 1 ppm or less range.
DA could also cause a similar (maybe slightly smaller) size after effect on settling: When switching from something like 10 V reading for some time to a short, it might take some time to come back all the way to zero. The effect should be larger in the non AZ mode, and might be to small to notice with AZ.

[szszjdb]

Hi,  Mr.Kleinstein ,

Thanks a lot!

For the long term drift, I had bypass the front/rear relay and replaced the K006 to a low EMF reed relay.  And I had opened the outer metal case  for easy testing. All this might take effect to the drift.

The most concern is still the INL of the ADC. What might be the next step?

Would like to have your advice! Thanks !

Best Regards,
szszjdb

[Kleinstein]

Finding the sources for INL in the ppm range is a really difficult task. It starts with the problem of reliably measuring INL in this range.
In the AZ mode I am not that sure the amplifier switching is not contributing to INL. At least in the old state some of the INL measured was due to switching artifacts. It might be worth repeating the INL test (compare to 3458 and turn over) with the modified amplifier.

One possible source of INL that came to my mind would be excessive ringing at the integrator input. After switching the S1024 current source, there will be some ringing of the OPs of the integrator. If the voltage at the integrator input would rise to above about 40 mV it would leave the linear range of the OP177 OP.  Ideally there would be very little voltage there (maybe 10 mV alternating spikes that decay over a few µs). It is hard to tell how parasitic capacitance, decoupling and charge injection of the switches would influence things. Also the distance to C210 is rater large. So the circuit around the integrator might not be that ideal.
There could be a reason for this distance: heating the capacitor could change the effect of DA.

Another point to check with the scope would be some of the ground points, e.g.:
Both sides of U504 GND buffer, the center of R201, the ground at Q205, GND at U301  (HC74 driving switches), GND side of C207, U211 Pin3.
There will be likely some ringing when Q204/Q205 switch - too much of this could be a problem.
The substrate voltage for switches could also be interesting (e.g. U204 pin 7).

Another possible test would be to see how much warming / cooling of R200 would change the offset: e.g. warm R200 with a local heat source (e.g. resistor as a heater at around 500 mW) a little and than watch the voltage change in non AZ mode measuring a short, when the heat source is removed. This give an indication on how sensitive R200 is to temperature.

Similar other thermal effects are possible: heat source that depend on the input voltage should be R200, Q200, U206, U207, R219, R220. Possible sensitive parts would be the ref. scaling (R232, R234) , R200 , R201 and also C206. For C206 a change in capacitance would not be a problem, but a speed up of the DA can likely have an effect in AZ mode. Still I doubt the heating would be enough to increase the temperature by some 5-10 K needed to get into the ppm range.

[szszjdb]

Hi,  Mr.Kleinstein ,

Thanks a lot!

I have checked the power supply and found 1-2mv noise in the -18V rail. Further checking with the scope ,found some swtching noise in it ,might coming from MUX gate switching. And there have a little more asymmetry for the +-27v ,which is about 0.6v.

I will check the other ponit tonight.

Best Regards,
szszjdb

[Mickle T.]

-18V source is zener based and don't have a linear regulator IC, like other rails.

[szszjdb]

Hi,  Mr.Kleinstein and Mr. Mickle T.,

Thanks a lot!

Further checked the INL, it is more like the old one and the 2 record for 6581 is tightly matched. So the drift is very small.

Checking the integrator with the scope both on the input and output side, nothing unusal found.

Also with the ZERO point of you mentioned above , it is just a noise background line and found nothing yet.

Will conduct the warming test tomorrow.

Would like to have your further advice!

Best Regards,
szszjdb

[Kleinstein]

The peaks at the integrator input are quite large. It looks like 50-75 mV peaks when the current source switches. This would be enough to leave the linear range of U205. So this might be in theory a point to possibly cause some linearity error, especially if these peaks change with input voltage.

One should treat the INL tests for both signs as a single data-set and thus get a single curve across zero. So just a single line fit. This should tell if for the positive side the error is more with the small voltages or the higher voltages.
It would be kind of expect the lower voltages to work  and than increasing deviation from about +5 V on. I put a few point together and it looks like this.

Anyway what changes at around + 5 V ? 
At around that voltage there was some oddity in the positive side input current. I have not found a positive side discharge test with the modified amplifier.

With the modified amplifier the negative side readings might have changes a little, as the bias is lower now. How is the 10 V-> 1 V transfer and the 1 M resistor test working now ?

[szszjdb]

Hi,  Mr.Kleinstein ,

Thanks a lot!

I reworked the INL data and did find the oddity arround +5v ,where the 3458 performed normally at that point. But I found nothing strange in the discharge curve arroud +5v. It seems that the error is coming from ADC itself.  Further comparing the total INL with the ADC INL curve, there have similar shape but smaller error in scale. So how is your comments?

The  transfer  error  are like the old one in DCV mode and are improved much from 200ppm to 20ppm in OHM mode. Might benefit from the modifying of the OPs.

Best Regards,
szszjdb

[Mickle T.]

The  transfer  error  are like the old one in DCV mode and are improved much from 200ppm to 20ppm in OHM mode. Might benefit from the modifying of the OPs.

This is an excellent result! Could you list all the changes made?