DIY highly linear 12-bit PWM digital-analog-converter, pointers please

[RandallMcRee]

Nice, very cool.

Can you describe your circuit a little bit? I can't seem to make out the details (or they are missing?). Where is the PWM signal originating? You are using a MAX4544 switch?

What kind of filter is that?

Thanks!

[MasterT]

Pwm-dac consists of 1 OPA + 1 switch SPDT shown in the lower side of the circuits. OPA is dual AZ precise 2uV from microchip, lowest price for quality I could find. First stage is a buffer for reference voltage, obviously. Second stage is an integrator - to smooth out rectangular pwm signal coming from the switch, max4544. Switch is driven on pin 7 (look at the pics, blue wire) from arduino Mega2560 - Timer 5 -> pin 46 channel a, fast PWM mode 14, Switch pin 1 - ground, pin 2 - output, connected to integrators input, pin 3 - reference voltage (buffered.) Configuration of the second stage is inverting, but it doesn't matter, there is no issue to invert PWM in software. I'm using single power +5V, test doesn't go to 0, there is 2 mVolts minimum voltage from OPA - unloaded.
Linearity equations show gain slightly over 1.0 -> not bad for ordinary 5% resistors (100k). Temperature stability is not tested at all, sure the would be high drift. 4 resistors presumed to be  arrays to keep thermal tracking, and certainly some circuitry  modification 'd be necessary, right now its in its simplest ever form.  Switch thermal Ron runaway is the primary problem I could envision at this point, so I already mention it somewhere.

More updates 

Arduino is very cool, I can do a testing with one click a button. Curiosity gets me to modify a circuit, instead of max4544 -precise, low leak, break-make, low injection bla-bla-bla, I put sn74hc4066. It tooks some efforts to modify a software, since chip is 4x spst, and to make a spdt out of two spst I need two pwm driver with safe time guard interval. AtMega doesn't have such feature internally, so have to program two phase offset-ed timers. 
Results:

Linear:      y = 1.000782 * x  -249778.296875
Linear:      y = 1.000425 * x  -247027.531250

   bin_C   uVolt   5717a   error   er_uV   pwmD   error   er_uV

   16384   128000   -233389   -7   -54   -230655   -18   -140
   32768   256000   -216990   -5   -39   -214261   -15   -117
   49152   384000   -200591   -3   -23   -197866   -11   -85
   65536   512000   -184193   -1   -7   -181473   -9   -70
   81920   640000   -167794   +0   +0   -165077   -4   -31
   98304   768000   -151396   +1   +7   -148684   -2   -15
   114688   896000   -134998   +2   +15   -132287   +3   +23
   131072   1024000   -118600   +3   +23   -115894   +5   +39
   147456   1152000   -102203   +3   +23   -99503   +5   +39
   163840   1280000   -85805   +5   +39   -83109   +8   +62
   180224   1408000   -69407   +6   +46   -66714   +13   +101
   196608   1536000   -53009   +7   +54   -50320   +16   +125
   212992   1664000   -36613   +6   +46   -33928   +17   +132
   229376   1792000   -20218   +4   +31   -17537   +17   +132
   245760   1920000   -3822   +4   +31   -1145   +18   +140
   262144   2048000   +12574   +3   +23   +15245   +17   +132
   278528   2176000   +28969   +1   +7   +31633   +14   +109
   294912   2304000   +45364   +0   +0   +48020   +10   +78
   311296   2432000   +61761   +0   +0   +64412   +11   +85
   327680   2560000   +78157   -1   -7   +80802   +10   +78
   344064   2688000   +94553   -1   -7   +97193   +10   +78
   360448   2816000   +110949   -2   -15   +113579   +5   +39
   376832   2944000   +127345   -3   -23   +129968   +3   +23
   393216   3072000   +143741   -4   -31   +146355   +0   +0
   409600   3200000   +160139   -3   -23   +162737   -9   -70
   425984   3328000   +176536   -2   -15   +179128   -9   -70
   442368   3456000   +192936   +0   +0   +195514   -14   -109
   458752   3584000   +209331   -1   -7   +211903   -16   -125
   475136   3712000   +225728   -1   -7   +228292   -18   -140
   491520   3840000   +242126   +0   +0   +244674   -27   -210
   507904   3968000   +258523   +0   +0   +261058   -34   -265

Its talks for itself, polynomial second degree - two column on the right side, error in 19-bits count and error in micro-volt. Not too bad, about 15-bits linearity, but now we know that switches are not the same. MAX4544, probably can do better than 18-bits, at this time I can't be sure that my ADC is not the one who is not linear.

[Andreas]

Hello,

thanks for the comparison.
I made a diagram out of it (since a picture tells more than 100 lines of tables

If you look closer then you see that the 5717 is not repeatable in both measurements (at the highest output voltage).
I fear that for more repeatable results you will to have to replace the breadbord (many undefined contacts) by at least a (soldered) perfboard.

with best regards

Andreas

[MasterT]

Hello,

thanks for the comparison.
I made a diagram out of it (since a picture tells more than 100 lines of tables

If you look closer then you see that the 5717 is not repeatable in both measurements (at the highest output voltage).
I fear that for more repeatable results you will to have to replace the breadbord (many undefined contacts) by at least a (soldered) perfboard.

with best regards

Andreas

Yes, I know that results is reliable to no more than 16-bits, and max5717a is also only 16-bits. Simpy switching power on/off I observed that all circuits need 5-10 minutes just to settle down noisy data. DS for DAC doesn't specify "warm-up" timing, but it is  quite long, definitely not a few  seconds.
 I'm experimenting , replacing  switches and opa, so soldering is not an option. 
I repeat my tests with sn74hc4066, cd74hc4066,  max4542 and ts5v330c.  All of them produce jerky results, interesting that max4542 (dual NC spst) is noisy as the others, and it tells me that I can't easily compare results from different configuration - 1 pwm or 2 pwm with safe guard timing (1 clock on arduino 62.5 nsec). Obviously, 2  phase shifted pwm would create a random waves along breadboard, and even if its soldered, it'd be much more complicated to design a board, with 3-4 layers , separate grounds etc. SPDT break-before-make switches seems the best option to make good pwm dac w/o a headache.

[MasterT]

More updates. I find a worst test case scenario, CD4052, marking TI , but I get a pack of 10 from aliexpress long ago for a buck ot two, so could be anything except TI. Measuring Ron resistance  with multi-meter shows 300-560 OHm . And unbelievable, this simple integrator circuits prints

ADS1232.
   Linear: y = 0.999580 * x -261467.187500
   Linear: y = 0.995693 * x -257465.093750
   bin_C   uVolt   5717a   error   er_uV   pwmD   error   er_uV
   8192   64000   -253286   -7   -54   -249305   +3   +23
   24576   192000   -236908   -6   -46   -232992   +2   +15
   40960   320000   -220528   -3   -23   -216679   +2   +15
   57344   448000   -204148   +0   +0   -200369   +0   +0
   73728   576000   -187772   -1   -7   -184060   -5   -39
   90112   704000   -171392   +1   +7   -167744   -2   -15
   106496   832000   -155014   +1   +7   -151430   -2   -15
   122880   960000   -138637   +1   +7   -135111   +3   +23
   139264   1088000   -122259   +2   +15   -118799   +1   +7
   155648   1216000   -105881   +3   +23   -102486   +1   +7
   172032   1344000   -89504   +3   +23   -86169   +4   +31
   188416   1472000   -73127   +3   +23   -69859   +1   +7
   204800   1600000   -56749   +4   +31   -53549   -1   -7
   221184   1728000   -40372   +4   +31   -37238   -4   -31
   237568   1856000   -23996   +2   +15   -20922   -1   -7
   253952   1984000   -7619   +2   +15   -4606   +0   +0
   270336   2112000   +8757   +1   +7   +11707   +0   +0
   286720   2240000   +25134   +1   +7   +28019   -1   -7
   303104   2368000   +41510   +0   +0   +44330   -3   -23
   319488   2496000   +57887   +0   +0   +60643   -4   -31
   335872   2624000   +74263   +0   +0   +76958   -2   -15
   352256   2752000   +90640   +0   +0   +93272   -1   -7
   368640   2880000   +107017   -1   -7   +109587   +0   +0
   385024   3008000   +123394   -1   -7   +125900   +0   +0
   401408   3136000   +139771   -1   -7   +142215   +0   +0
   417792   3264000   +156147   -2   -15   +158531   +3   +23
   434176   3392000   +172526   +0   +0   +174844   +2   +15
   450560   3520000   +188904   +0   +0   +191157   +2   +15
   466944   3648000   +205279   -1   -7   +207470   +2   +15
   483328   3776000   +221657   +0   +0   +223784   +2   +15
   499712   3904000   +238032   -3   -23   +240092   -2   -15
   516096   4032000   +254411   -1   -7   +256408   +0   +0

 Switch, that was design 40-50 something years ago, stays in close match with modern bla-bla-bla extremely overpriced piece of .. silicon. Don't rush to spend $3+ on low R-on (max 4652 4OHm)  , test shows that cd4052 is much better!   
 

[RandallMcRee]

Thanks, again, MasterT.

I have spent some time this weekend looking at switches. One thing I notice is that the on/off times are pretty slow (especially with low charge injection switches).

Could you test the linearity at the lowest range (meaning narrowest pulses)? Seems like a switch like the hc4066 simply cannot be linear with pulses of less than 200nS or so.

But there are faster switches, like the ahc4066 (30ns rise) and I will also try the Hitachi TC7W66FU. Personally, I'm not trying to minimize cost, but, sure, who wants to spend more than necessary.

A different approach (I thank amspire for this) is to power a logic package from a precision +5v reference and use those gates to drive the PWM filter. Perhaps that approach would get better results especially in the lower range. Will need to compare with the switch approach.

Just fyi, one of my goals is to use an LTZ1000 reference. Obviously, this makes the native vref be 7.2v. So the main reason I am going to try the Hitachi switch is that you can power it from +12v and directly use vref from the LTZ (or a +10v reference). Using logic gates and also ahc4066 means stepping down 7.2 to 5v which is just another source of error. So, we'll see.

Attached: proposed filter.

[amspire]

There is a range of very high speed cmos chips from Potato Semicinductor

http://www.ibselectronics.biz/active/potato-semiconductor.htm

The PO74G00A for example has a 0.8ns rise and fall time and a 1.5ns high and low propagation delay. They are only 3.6V chips but they accept a 5.5V logic drive. The actual absolute maximum operating voltage is 4.6V.

I just haven't seen anyone sell them so I do not know the price.

Edit: The PotatosSemi parts are available from an eBay store:

http://stores.ebay.com/potatosemi_W0QQsspagenameZMEQ3aFQ3aSTQQtZkm

$3 for a basic logic chip.

I just ordered a few of these 8 pin clock buffer chips: http://www.potatosemi.com/potatosemiweb/datasheet/PO74G38072A.pdf
https://www.ebay.com/itm/38074-GHz-CMOS-Output-Clock-buffer-IC-8pin-SOIC-QTY-1-/330378214526

The chips come with extra Vcc and GND pins that probably helps reduce errors.

[RandallMcRee]

Folks, I have looked into the Keithley 263 (Thanks Alex Nikitin). It uses a gate driver and two 2N7000 mosfets. These have 10ns rise/fall specs. So perhaps Keithley found "normal" analog switches not up to the task?

[amspire]

One of the things makes sense with using a logic IC powered from the reference voltage is that the PWM needs buffering anyway. The only filtering I needed on the PWMs in that earlier post was simple multistage RC filters which behave pretty close to ideal.

Since you need a buffer, you can use a low-offset or a auto-zero opamp along with something like the Linear Technology LT5400A-1/LT5400B-1 4x 10K resistor array to boost the voltage by a factor of 3 or 4 with a 0.01%/0.025% accuracy, 0.2ppm/C coefficient and 2ppm/2000hours long term stability.

If you can live with the "B" grade array, it is almost a third the cost.

[MasterT]

Could you test the linearity at the lowest range (meaning narrowest pulses)? Seems like a switch like the hc4066 simply cannot be linear with pulses of less than 200nS or so.

 You can calculate pulse width out of arduino's printout, it's in bin_C , all it takes is convert 19bits back to 12bits and multiply 62.5 nanoseconds arduino clock cycles. So 8192 in the first line corresponds to 8192 /128 *0.0625 = 4 useconds, and 516096 to 252 usec pulse width PWM. You are asking below 200 nsec, in arduino cycles it's only 3 clock periods.
Here is the measurement from the beginning. CD4052 chip, is the slowest one in my collection. Sure it's not linear, I don't think there is an issue. Arduino could generate not exactly 4096 clock cycles, but 4196, so cutting 100 from the start (signal conditioning after the dac) we can easily solve a problem with offset error

[Kleinstein]

Folks, I have looked into the Keithley 263 (Thanks Alex Nikitin). It uses a gate driver and two 2N7000 mosfets. These have 10ns rise/fall specs. So perhaps Keithley found "normal" analog switches not up to the task?

The Keithley design is rather old. In the early days the choice of CMOS switches was not that large and not that many low R_on switches. In many respect the R_on could be the more important factor than the switching speed. Speed comes in mainly indirectly, as higher speed usually also means lower jitter. A difference in R_on is mainly what effects linearity.

The CD4052 is not only lower speed but also higher R_on.

[MisterDiodes]

RandallM:  Just out of curiosity - you want to build a 12-bit DAC that is 24-bit accurate using PWM... Just exactly how do you plan on measuring a physical circuit to verify proper operation?  Measuring to better than 20 bits (1ppm) <absolute value> is not easy and requires something equivalent to perhaps several 732-grade Vrefs. if you're after long time frame stability - if that's what you need.  Measuring <ratios> at higher than 20 bits is a challenge too - be careful of the equipment you're using to measure.

Or is this just a thought exercise for fun?

You do realize you can buy 16 / 18 bit DAC's off the shelf for < $5 that will guarantee you 12-bit accuracy without doing anything else (and give you some "bit room" to caress a compensation curve)...of course diffused resistors will add a bit of noise - but what is the budget for this device you're planning (in dollars - or are you going typical EEVblog style => cheap as possible??) and what is the allowed noise budget  and long term drift rate???

Coming up with answers to those questions first will help fence in the design later on.

PWM methods can work to a point - but just remember getting rid of noise is sometimes harder than not generating noise in the first place ( Don't forget the impact of noise in your power rails and EMI problems with fast edges).  The switches and noise injection / Ron are always a weak link in the chain here as you are finding out.  You also might look at the higher end JFET switch designs that will work well at 7~15VDC ranges with very low charge injection.  They won't be cheap, but precision doesn't come free either.

[RandallMcRee]

RandallM:  Just out of curiosity - you want to build a 12-bit DAC that is 24-bit accurate using PWM... Just exactly how do you plan on measuring a physical circuit to verify proper operation?  Measuring to better than 20 bits (1ppm) <absolute value> is not easy and requires something equivalent to perhaps several 732-grade Vrefs. if you're after long time frame stability - if that's what you need.  Measuring <ratios> at higher than 20 bits is a challenge too - be careful of the equipment you're using to measure.

Or is this just a thought exercise for fun?

It is true that I do not have the equipment needed to verify performance. But, I do intend to build a PWM and, hopefully, over time, with others help, can do some verification. The whole idea (in my mind, even if not clear from goals) is to create something that is 24-bit linear by design.  If the particular PWM design does not meet its goals then again, hopefully, the design can be updated so that it does. I do plan on having a 16-bit DAC on hand to compare directly with the PWM. Its an AD5546CRUZ.

This is for fun, but its not solely a thought exercise.

[amspire]

RandallM:  Just out of curiosity - you want to build a 12-bit DAC that is 24-bit accurate using PWM... Just exactly how do you plan on measuring a physical circuit to verify proper operation?

It depends on the reason for asking for the 24-bit linearity. If the reason was to have voltage increments for the 12 bit D/A that were uniform in size to within 0.1%, then that is something PWM does much better then a 12 bit D/A. So if 0xFFF is set to better than 0.1% accuracy, then 0x001 is also 0.1% accurate. For a 12 bit D/A, 0x001 would probably have around a 50% accuracy.

Also a PWM can be very cheap. I have used PWM where I want very precise adjustability (ie high resolution but not high accuracy) without the cost of 24 to 32 bit D/A chips. One of the evils in going from analog to digital is you often go from a linear stepless adjustment to discrete steps. For example, modern power supplies that can often only manage 1mV steps compared to older analog supplies with a multi-turn FINE voltage control that goes well below 1mV in resolution.

[MisterDiodes]

RandallM:

Any thoughts on what your goal noise density at the output? At what freq??  And at what dollar budget are you shooting for?

Just bear in mind - at one low end of the spectrum you've got a cheap & simple DAC chip that doesn't contribute switching noise but not as accurate as you'd like - at the extreme other end, for true 23~24 bit accuracy you've got this for a target accuracy spec inspiration @ dollar budget cost:

https://www.ietlabs.com/kvd-700.html

...A true DAC that works to DC and includes a built-in 7-digit non volatile memory.  Too bad it uses foil resistors, that makes it slightly more noisy than PWW, but you can't have everything for USD $30,000 

EDIT: Fluke's USA List Price on a 720a is currently USD$ 46,255.  So if you consider that an approximate 24-bit accurate DAC - that gives you an idea that a PWM method budget might be somewhere below that...  That's a pretty big ballpark range.

I would suggest this:  I would look at a PWM methods where you try for 16 / 18 / 20 bits true accuracy first, on real circuits, which is more in the realm of practical.  You will find out where theory ends and reality begins...  And that will guide you on to what's required for tighter accuracy.

At around 20~21 bits - You'll find that's about where the never ending switch & clock stability problems become more apparent, and you'll also see that pesky switch TC and noise effects creep in.  Beyond that you'll usually find a steep wall where it's harder (and much more expensive) to maintain real accuracy.  Resolution is usually meaningless without accuracy for real metrology applications.

If you're going for "cheap" - yes, that's always nice but generally you get what exactly you pay for.  Sometimes that's plenty enough depending on what you really need.

You'll also find out along the way that the often-quoted EDN design idea for a 32-bit DAC was a complete fantasy - and you'll learn why.

Have fun!!

[RandallMcRee]

I modified post #1 with a proposed schematic. Its a standalone PWM although I assume an arduino or similar loads a counter with some desired value.

The kicad schematic is on github at: https://github.com/RMcRee/12-bit-linear-pwm

I went with the amspire idea of using a 74HC to directly drive the filter. After examining and buying many analog switches I thought the simplicity of that idea was too tempting not to try.

Posting png here so you don't have to flip back to the start...

[amspire]

You have gone for 74FCT and 74F chips - I assume for their speed. The 74F chips in particular use a lot of power and could add a lot noise into the board.

You can eliminate the need for super-fast IC speeds and improve timing accuracy by just adding one synchronous latch before the 74HC74. The latch resyncs the transitions to the clock edges.

The 74FCT163s clock on a rising edge. Just set the output latch to clock on the falling edge. You only need enough speed then to reach the correct state in 50 ns instead of trying to find sub 10ns speeds.
Edit: My mistake, I see you are using the output 74HC74 also as a latch. There could be some feedthrough from the clock and the non latched data inputs to this output IC. I usually have the latch and output IC separate so the output IC only sees a very precisely clocked input and nothing else.

If the output is latched, do you need 74F chips?

[RandallMcRee]

Yes, the 74F series is scary around precision stuff. I got there like this:
10Mhz is 100nS between clock transitions (budget).
An 74HC74 latch needs 18nS of setup time (82 nS left)
The fct163 has prop. delay of 12nS (so 70ns remaining).
The simple three cascaded 74hc85 requires three propagation delays, but one prop is 50nS worst case (over budget). The 74F85 gets those three delays in 14+9+9=32nS.

Hmm, what about using the hc688 and the A=B output?
hc688 prop delay is 51 nS. Need NAND gate (can't use En to cascade!) so that is another 9nS, so 60 nS. So, I think that is just possible. I'll give that a try....

Thanks!

[Kleinstein]

What is the purpose of the discrete logic PWM generation ? The µCs are supposed to be about as fast as 74HC logic. If you have some doubt on the clock stability of the µC (e.g. µC with internal PLL), one can add an extra synchronizing flip-flop after the µC.

When it comes to linearity, one has the think about the output resistance and the loading to the switches part. The filter shown below would be a load that depends on frequency / PWM setting.

At the sub-ppm end also resistors may not be as linear as needed. Self heating alone can make the resistors nonlinear. So the filter shown may not be such a good solution as it uses several resistors that need to be linear.

[amspire]

What is the purpose of the discrete logic PWM generation ? The µCs are supposed to be about as fast as 74HC logic. If you have some doubt on the clock stability of the µC (e.g. µC with internal PLL), one can add an extra synchronizing flip-flop after the µC.

Randall knows that. He just wanted to do it using discrete logic.

I did some tests on jitter with an atmega324P and it is very good. Forgotten the numbers but it is sub-nanoseconds as long as you use the high power clock. The low power clock is rubbish.
So none of that was ever an issue here. I guess Randall liked something that just worked without any programming.

When it comes to linearity, one has the think about the output resistance and the loading to the switches part. The filter shown below would be a load that depends on frequency / PWM setting.

At the sub-ppm end also resistors may not be as linear as needed. Self heating alone can make the resistors nonlinear. So the filter shown may not be such a good solution as it uses several resistors that need to be linear.

You are talking about resistance changes due to self-heating over 400us. Any resistance change over a longer period doesn't matter. I doubt the change over 400us is very much. I have played with metal film with very high precision and you could see drifts such as 10ppm/second on applying a 5V load. Say it is 100ppm/second. That would equate to 0.04ppm over 400us. That is down in the noise level.

As far as the filter is concerned, the PWM frequency is constant - at 2.44KHz I guess. These third order Salen Key filters work pretty well here as the worst of the HF noise is handled by the initial RC filters. By the time the signal reaches the opamp, the HF components are very attenuated so the opamp can usually handle it very well. He could get down to 24 bit resolution with multi RC stages without any active filter but you are talking about settling times of about a second. Randall wanted it 10 times faster.

The cmos output is used mostly at 0-4mv or 4.996 - 5V. Over such a small variation, the channel resistance changes very little. It also doesn't matter if the channel resistance changes with temperature if both the sink and source channels increase equally with temperature.

The main issue is the difference in source and sink channel resistance. It will have an effect. If it is 10 ohms, then with the current parts chosen, you can get a one 12 bit count error midscale. If an extra RC stage was added with a 100K resistor at the start, this might be reducible by a factor of 4.

Again I think Randall knows this. I think the idea is to build something - then he can play with it. the Mark I design will work pretty well and if he is lucky, it may even work better then expected. But he has hundreds or even thousand of different cmos devices he can look to as the PWM switch. It can just be added after the 74HC74. The PWM switch is the critical part. I think Randall didn't want to start with an expensive solution that might not work any better.

[BravoV]

Subscribed.

[RandallMcRee]

Thanks, Amspire. Yes, you represented the project goals well.

1) The counter stuff is to make it stand-alone. Presumably, anyone who looks at the project can say to themselves "oh hey I don't need all of that counter stuff". But I envisioned this sitting, alone and lonely, in a lab happily generating a precision voltage while the microcontroller is being flogged by an update. Also, you get to use your ovenized, weaponized, cesium-locked, rubidium-checked 10Mhz clock. It's lonely too, just sitting on the shelf.

2) This is the first time I have ever heard that a filter might need low TCR resistors. I hope not. But if so, that would actually be a cool learning experience. Not just for me, I suspect. It seems like the 9.1k/Ron ratio is the important quantity. We could also simply scale that resistor up, that's easy. Noise increases so there is a tradeoff, there. But the ratio is ~ 1000:1 I think.

3)  Yes, I actually bought many analog switches but then I could not see any benefit in complicating the circuit. So this will establish a baseline. If there is a benefit we should be able to quantify it. I could not find an analog switch that met *all* of these criteria: ron<2ohms, Ton < 10nS, control levels hc compatible, source-drain voltages 12v or more, ideally +-15v.

Thanks

[ch_scr]

Regarding the ATMega pwm stability i have a story to share, a while ago i tried to do low frequency sine wave generation via dds & pwm on an ATMega8. 12 Bit pwm, max frequency around 10-20 Hz. Sinewave from a lookup table, as many points as i could fit inside the Flash. I used the Scopes FFT to check purity after the filter, and sure enough found my pwm switching frequency there, very surprising for me together with what looked like sidebands. After some trying, i switched of my dds loop and had only the PWM going on a fixed value; sidebands gone. Got the DDS going again, sidebands where back. I found a discussion online hinting that updating the value of the pwm output value (comperator register) is done before the beginning of a new counting cycle (the value is loaded from the shadow register to the actual comparing register). As this takes time, the PWM cycle time would be slightly longer after an "update event".

[RandallMcRee]

Version 2, using HC688 and JK flip flop.

[MisterDiodes]

No. Not close to an accurate DAC if I'm looking at your schematic correctly.

Learn the limitation of 74AC logic family on your PWM:  For a PWM DAC to be accurate, you have to accurately PWM  switch between Vref and 0 volts (usually - and I think that's what you are assuming might magically happen here). On your circuit you're switching between some unknown high voltage of around VRef-0.25V to VRef-.1V typical (depends on manufacturer, temperature, load etc.) and on low side you're have an unknown voltage somewhere between 0 to 0.25V.  With a strong TC by the way.

Notice the Ti datasheet will typically only list the MIN and MAX Vol and Voh...that's not what a real CMOS 74xx output does when you have a non-zero load impedance.  Typically you never reach true zero volts or true Vref output voltage swing limits.

In other words, logic chips ain't real analog switches, and normally they are never used that way - and that's why.

Also look at your output filter.  That's why I was asking you about noise budget / and low TC.  It's a challenge to design op-amp filters that maintain very high DC accuracy at low enough noise to even reach true 18/20 bits, let alone 24 bits over even a small temperature range.  The resistors and caps specs aren't trivial, and look at the TC of your amps.

I suggest you go back and look at your analog switch requirements you listed and do a bit of research.  Learn why those specs you listed are hard goals to reach simultaneously in a solid-state switch.  You want fast switching, but high dv/dt on the gate means higher charge injection.  You want low RdsOn, but that isn't necessarily fast or low charge injection.  If you have low charge injection you'll tend to have higher RdsOn. Learn why that tends to be the case.  This is a great time to learn the physics involved and learn how to read "between the lines" on a datasheet.

Hint: Investigate how you drive a good Jfet switch with another one....

These are just some of the reasons why there are limits on the true accuracy of various PWM techniques for DAC applications.

Have fun!