DIY highly linear 12-bit PWM digital-analog-converter, pointers please

[RandallMcRee]

Folks,
I have seen references in the forum to the PWM method of building a dac, the main virtue (I think) being temperature independence. Having mostly assembled an R-2R 10-bit dac I can see that that would be highly desirable.

Goals:

• 10-12 bit resolution
• Linear, ideally 24-bit linearity
• Not fast, <10 changes per second
• Temperature independent DC output

The current plan goes like this:
10Mhz oscillator --> counter --> magnitude comparator -> flip-flop -> 3rd order LP filter@20Hz

The above rough sketch seems to meet the goals..I think. Is there a better way?

I'm not sure of the best way to take a flip-flop output and generate a good analog input to the low-pass filter. We obviously want a good VRef to dictate the analog high value and not any old arbitrary 5v. What is typical here? The simpler the better, right?! Things I have thought of so far are: CMOS gate powered by VRef, or perhaps some fast analog comparator.

What I don't think is needed: fancy ways to spread the noise spectrum around, ala spread spectrum switching, lfsr, etc.: because I think the 2400Hz 50% duty cycle ripple can be adequately filtered without resorting to that complication. Also, I've built lots of analog filters and that is like, my, sweet spot. So if a 5th order LP is needed, fine.

Thanks!
Randy
Update: 2/26/2018: proposed schematic. See https://github.com/RMcRee/12-bit-linear-pwm
Update: 2/27/2018: Use HC688, jk ff, show time budget.
Update 3/25/2018: Updated schematic to that actually built. Used 74hc595 to interface to arduino, in the end. Tested, works.

[duak]

I was thinking of buying a Tek PS5004 precision power supply recently and downloaded a block diagram from somewhere to see how it worked.   It has a 0-20 V output with 0.5 millivolt resolution and accuracy.  It uses switched current sources controlled by the PWM followed by a summing amplifier and 5th order filter.  I couldn't find a schematic to confirm the nuts n' bolts of the circuit though.

Best o' luck,

[Kleinstein]

For producing the PWM signal I would consider a small 8 bit µC (thus without an PLL), like PIC18, 8051 or AVR. They usually have HW for PWM up to 16 Bit inside. The Output stage an filter can be a bit tricky. Maybe have a look at the circuit of the Fluke57xx calibrators. There is somewhere a thread here to show how it looks like that include a circuit diagram. The output stage might work with CMOS switches like DG419 or similar. It still needs good buffering of the reference.

[ch_scr]

In a book on D2A converters i found this neat trick for PWM-DACs. It gets you a bit of noise-spreading / higher PWM frequency(s) for almost free, the almost being the type of digital comperator used. I have attached the rather explanatory illustrations.

[Mickle T.]

The design of such PWM DAC was recently submitted by adver on the forum radiokot.ru:
http://radiokot.ru/forum/viewtopic.php?p=3112844#p3112844
http://radiokot.ru/forum/viewtopic.php?p=3113890#p3113890 e.t.c.

Small Attiny25 with 8-bit PWM, software 3-order MASH, ADG419, OP177, 3-stage LP - that's all.

[Andreas]

It gets you a bit of noise-spreading / higher PWM frequency(s) for almost free

not for free. it is at the cost of linearity: the rising and falling edges are never the same duration.
And with this method you have a variable number of edges within one counter period.
If you aim for linearity: keep the number of edges low. (e.g. 100 Hz) and use symmetrical switches.

with best regards

Andreas

[ch_scr]

Darn! Theres always something out there to get you. Thanks for the explanation!

[David Hess]

We obviously want a good VRef to dictate the analog high value and not any old arbitrary 5v. What is typical here? The simpler the better, right?! Things I have thought of so far are: CMOS gate powered by VRef, or perhaps some fast analog comparator.

Instead of a gate, an analog switch which will normally be break-before-make is commonly used as the modulator.  Do not forget about keeping digital noise out of both the analog ground, power, and voltage references.

What I don't think is needed: fancy ways to spread the noise spectrum around, ala spread spectrum switching, lfsr, etc.: because I think the 2400Hz 50% duty cycle ripple can be adequately filtered without resorting to that complication. Also, I've built lots of analog filters and that is like, my, sweet spot. So if a 5th order LP is needed, fine.

The analog filter's settling time will limit usable update rate.

[amspire]

A Hellene and myself had a discussion with code about a 20+ bit PWM D/A using Atmega328 and ATiny chips. The time constant here was more like 1 second, but it is not hard to change for less resolution. You should be able to easily do a 16 bit PWM D/A with a 10/second rate.

The linearity even with a simple breadboard test was extremely good. In my test, I just used a cmos 74HC NAND gate IC powered directly by a 5V reference IC as the PWM output buffer into a R/C pair. Then all you need is a few more RC stages to reduce the ripple. You would probably need a buffer IC.

The Atmega328P has a very low jitter clock, as long as it is not run in low power clock mode.

The discussion started here:

https://www.eevblog.com/forum/projects/general-purpose-power-supply-design-7488/msg99807/#msg99807

Linearity tests:

https://www.eevblog.com/forum/projects/general-purpose-power-supply-design-7488/msg106218/#msg106218

[Andreas]

Small Attiny25 with 8-bit PWM, software 3-order MASH, ADG419, OP177, 3-stage LP - that's all.

Thanks for the cirquit. But in this case it is a 7->10V transfer
so the linearity does not play a role.
Only stability over time.
But for that application it seems to be a very tricky solution. 

with best regards

Andreas

[Kleinstein]

It gets you a bit of noise-spreading / higher PWM frequency(s) for almost free

not for free. it is at the cost of linearity: the rising and falling edges are never the same duration.
And with this method you have a variable number of edges within one counter period.
If you aim for linearity: keep the number of edges low. (e.g. 100 Hz) and use symmetrical switches.

with best regards

Andreas

There is no need to have the same speed for both edges. Unequal edges would give rise to an offset though, but there may be some offset due to charge injection anyway.

The important part is to have the same number of switching events and enough time between so that the circuit has settled (especially the reference buffers) - so no super fast pulses. Buffering the reference can also be important, as the switches can cause quite some dynamic load.
Matching of both switches can also be important.
For the switches one should have resonably low resistance as the switch resistance usually has a high TC.

[Alex Nikitin]

Folks,
I have seen references in the forum to the PWM method of building a dac, the main virtue (I think) being temperature independence. Having mostly assembled an R-2R 10-bit dac I can see that that would be highly desirable.

Goals:

• 10-12 bit resolution
• Linear, ideally 24-bit linearity
• Not fast, <10 changes per second
• Temperature independent DC output

The current plan goes like this:
10Mhz oscillator --> counter --> magnitude comparator -> flip-flop -> 3rd order LP filter@20Hz

Hi Randy,

Have a look at the Keithley 263 voltage source circuit.

Cheers

Alex

[RandallMcRee]

Thanks folks,
Looking into all of these suggestions....

Is this Keithley manual the right one?

https://doc.xdevs.com/doc/Keithley/263/263_901_01E.pdf

Will try to come up with a schematic and put it in post #1.

[Alex Nikitin]

Is this Keithley manual the right one?

https://doc.xdevs.com/doc/Keithley/263/263_901_01E.pdf

Yes, page 170.

Cheers

Alex

[Magnificent Bastard]

The DG636E looks like a good candidate for this sort of thing.

[zhtoor]

or an H11F1 optomos with ZERO charge injection, if speed is not an issue.

-zia

[Kleinstein]

For PWM with switching at the reference side charge injection should not be such a big issue, though it helps to keep the dynamic load to the reference low. With a dual switch one could use the second one to switch the opposite way and this way keep the reference current approximately constant.

[MasterT]

I don't think, that simple circuit like Ref->Switch->LPF  can provide linearity better than 15-bits or 10 ppm. There are two issues with the switches, Rds variation by temperature & voltage (non linearly) from one end, plus leakage current on the other side.  Using a current source as a feed to an analog switch may be a nice trick to cancel Rds , though preventing a current source out of saturation during the "off" time could be even more problematic.
 Real time monitoring of Rds could be a solution, using more switches for re-mapping  primary  switch to the measuring path, and supplementary ADC to do a measurement itself. Plus software correction of the PWM duty circle based on actual Rds. Thinking aloud.

[Kleinstein]

With the switches choosing between 2 reference levels (0 and U_ref), there should be very little problem with leakage and R_on variations with voltage. However there still is the problem of Rds variations with temperature and a different Rds for the positive and negative side (because they are at a different voltage). So it takes some extra effort (e.g. careful Rds matching, extra current sources so that the switched that set the voltage don't see much current), but a good pair of switches is a first step.

[Andreas]

Hello,

Is this Keithley manual the right one?

https://doc.xdevs.com/doc/Keithley/263/263_901_01E.pdf

don´t know how the Keithley cirquit behaves in comparison to the EDN cirquit mentioned here:
https://www.eevblog.com/forum/metrology/stacking-ad587s-for-higher-output-voltage-(20v-30v-etc-)/msg1320513/#msg1320513

At least with modern processors like e.g. ATMega1284 or PIC24FV32KA304 it takes much less components to build a 16 Bit PWM.

The DG636E looks like a good candidate for this sort of thing.

did you make a comparison how linear it behaves compared to the MAX4052A?

with best regards

Andreas

[Magnificent Bastard]

The DG636E looks like a good candidate for this sort of thing.

did you make a comparison how linear it behaves compared to the MAX4052A?

with best regards

Andreas

Nope.  Just found it searching for the "least evil" SPDT switch I could find.  This one is a balance of being fast, has relatively low on resistance, good on/off resistance matching, and very low charge injection.  Taking all of those things into account, it has a very high figure of merit.  I think the linearity only matters if you are passing a variable analog voltage through it, but in this application it is more of a "digital" thing (where the analog voltage being switched does not vary).  If you are switching between some fixed voltage to another fixed voltage, and the power supply voltage does not change much, then this is the best switch I have found that is a "buy it and it just works" thing.  I can make a far better SPDT switch using discrete parts (good enough for 8.5 or 9.5 digits), but I don't think that is in line with the spirit of this thread, which is about 12-bits of accuracy.  I'm probably not going to build anything, I just mentioned it because I thought it might be useful to someone looking for a "good" (small, simple, and inexpensive) switch, ~US$1.53 at DigiKey.  You're welcome to make the comparison yourself, I will just watch...

[Andreas]

  You're welcome make the comparison yourself, I will just watch...   

I fear we will never know it ...
If all are only watching.

with best regards

Andreas

[RandallMcRee]

The switches I have on hand (which makes them top candidates in my mind!) are the DG411, the ADG1411 and 74hc405x. I picked the ADG1411 for a different application where Ron was important (1.5ohms), but the charge injection is 20pC, typical. Not sure what the interplay will be between Ron and charge injection.

That DG636E certainly has some great specs, especially for the price. So perhaps I will try that one, you can never have too many switches.

BUT the problem with trying switches is that they all have different pinouts. So I cannot promise to try them all...

[MasterT]

It was easier than I thought.  Inspired by LTC1043, and app. note from LT.
Here is the setup. Since I don't have good quality equipment to test linearity over 12 bits, my multimeter has only 1 mV resolution below 4V at the best,  I use ADS1232 board from aliex.  I also install  MAX5717A DAC (16-bits, 1 LSB INL) in parallel as a verification/ reference path. Arduino Mega is running pwm driver, reading ADC, updates both DACs and switching multiplexer in front of ADC, plus searching linear regression and print an error over serial monitor. 

Everything on a breadboard, a lot of noise, but results is quite good for start.

Linear:      y = 1.000762 * x  -249761.562500
Linear:      y = 1.004887 * x  -249921.296875

   bin_C   uVolt   5717a   error   er_uV   pwmD   error   er_uV

   16384   128000   -233375   -9   -70   -233456   +1   +7
   32768   256000   -216973   -4   -31   -216989   +4   +31
   49152   384000   -200576   -3   -23   -200524   +5   +39
   65536   512000   -184176   +0   +0   -184058   +7   +54
   81920   640000   -167779   +0   +0   -167594   +6   +46
   98304   768000   -151381   +1   +7   -151132   +4   +31
   114688   896000   -134982   +4   +31   -134674   -1   -7
   131072   1024000   -118585   +4   +31   -118210   -1   -7
   147456   1152000   -102187   +6   +46   -101747   -2   -15
   163840   1280000   -85791   +5   +39   -85284   -3   -23
   180224   1408000   -69394   +6   +46   -68815   +1   +7
   196608   1536000   -52998   +5   +39   -52347   +5   +39
   212992   1664000   -36601   +6   +46   -35885   +3   +23
   229376   1792000   -20206   +4   +31   -19422   +2   +15
   245760   1920000   -3811   +3   +23   -2959   +1   +7
   262144   2048000   +12586   +3   +23   +13504   +0   +0
   278528   2176000   +28979   +0   +0   +29965   -2   -15
   294912   2304000   +45373   -2   -15   +46428   -4   -31
   311296   2432000   +61771   +0   +0   +62892   -4   -31
   327680   2560000   +78166   -2   -15   +79356   -4   -31
   344064   2688000   +94563   -1   -7   +95820   -4   -31
   360448   2816000   +110959   -2   -15   +112284   -4   -31
   376832   2944000   +127354   -3   -23   +128747   -5   -39
   393216   3072000   +143752   -2   -15   +145212   -4   -31
   409600   3200000   +160148   -2   -15   +161677   -3   -23
   425984   3328000   +176545   -2   -15   +178144   +0   +0
   442368   3456000   +192942   -1   -7   +194610   +1   +7
   458752   3584000   +209341   +0   +0   +211077   +4   +31
   475136   3712000   +225736   +0   +0   +227544   +7   +54
   491520   3840000   +242130   -3   -23   +244009   +8   +62
   507904   3968000   +258524   -5   -39   +260471   +5   +39

Columns:   
1. bin_C- binary code, scaled to 19-bits, same as ADC, I don't need 24-noisy bits, 19-more than enough.

2. uVolt - microvolts associated with 4096mV reference
3. raw ADC data from    5717a   
4. error in 19-bits scale
5. error in microVolts   er_uV   
6. raw ADC data from pwmDAC
   error
   er_uV

PWM set to 3.9 kHz, based on 16 MHz / 4096 (12-bits).  MAX5717A getting 16-bits, pwmDAC - 12, to keep settling time low. I will check more on this tomorrow probably.

[MasterT]

More pics and more tests done. Overall close to 18-bits linearity +-1 bit INL.  Ripple voltage is quite high, luckily sigma-delta adc has no issue to filter it out.

[RandallMcRee]

Nice, very cool.

Can you describe your circuit a little bit? I can't seem to make out the details (or they are missing?). Where is the PWM signal originating? You are using a MAX4544 switch?

What kind of filter is that?

Thanks!

[MasterT]

Pwm-dac consists of 1 OPA + 1 switch SPDT shown in the lower side of the circuits. OPA is dual AZ precise 2uV from microchip, lowest price for quality I could find. First stage is a buffer for reference voltage, obviously. Second stage is an integrator - to smooth out rectangular pwm signal coming from the switch, max4544. Switch is driven on pin 7 (look at the pics, blue wire) from arduino Mega2560 - Timer 5 -> pin 46 channel a, fast PWM mode 14, Switch pin 1 - ground, pin 2 - output, connected to integrators input, pin 3 - reference voltage (buffered.) Configuration of the second stage is inverting, but it doesn't matter, there is no issue to invert PWM in software. I'm using single power +5V, test doesn't go to 0, there is 2 mVolts minimum voltage from OPA - unloaded.
Linearity equations show gain slightly over 1.0 -> not bad for ordinary 5% resistors (100k). Temperature stability is not tested at all, sure the would be high drift. 4 resistors presumed to be  arrays to keep thermal tracking, and certainly some circuitry  modification 'd be necessary, right now its in its simplest ever form.  Switch thermal Ron runaway is the primary problem I could envision at this point, so I already mention it somewhere.

More updates 

Arduino is very cool, I can do a testing with one click a button. Curiosity gets me to modify a circuit, instead of max4544 -precise, low leak, break-make, low injection bla-bla-bla, I put sn74hc4066. It tooks some efforts to modify a software, since chip is 4x spst, and to make a spdt out of two spst I need two pwm driver with safe time guard interval. AtMega doesn't have such feature internally, so have to program two phase offset-ed timers. 
Results:

Linear:      y = 1.000782 * x  -249778.296875
Linear:      y = 1.000425 * x  -247027.531250

   bin_C   uVolt   5717a   error   er_uV   pwmD   error   er_uV

   16384   128000   -233389   -7   -54   -230655   -18   -140
   32768   256000   -216990   -5   -39   -214261   -15   -117
   49152   384000   -200591   -3   -23   -197866   -11   -85
   65536   512000   -184193   -1   -7   -181473   -9   -70
   81920   640000   -167794   +0   +0   -165077   -4   -31
   98304   768000   -151396   +1   +7   -148684   -2   -15
   114688   896000   -134998   +2   +15   -132287   +3   +23
   131072   1024000   -118600   +3   +23   -115894   +5   +39
   147456   1152000   -102203   +3   +23   -99503   +5   +39
   163840   1280000   -85805   +5   +39   -83109   +8   +62
   180224   1408000   -69407   +6   +46   -66714   +13   +101
   196608   1536000   -53009   +7   +54   -50320   +16   +125
   212992   1664000   -36613   +6   +46   -33928   +17   +132
   229376   1792000   -20218   +4   +31   -17537   +17   +132
   245760   1920000   -3822   +4   +31   -1145   +18   +140
   262144   2048000   +12574   +3   +23   +15245   +17   +132
   278528   2176000   +28969   +1   +7   +31633   +14   +109
   294912   2304000   +45364   +0   +0   +48020   +10   +78
   311296   2432000   +61761   +0   +0   +64412   +11   +85
   327680   2560000   +78157   -1   -7   +80802   +10   +78
   344064   2688000   +94553   -1   -7   +97193   +10   +78
   360448   2816000   +110949   -2   -15   +113579   +5   +39
   376832   2944000   +127345   -3   -23   +129968   +3   +23
   393216   3072000   +143741   -4   -31   +146355   +0   +0
   409600   3200000   +160139   -3   -23   +162737   -9   -70
   425984   3328000   +176536   -2   -15   +179128   -9   -70
   442368   3456000   +192936   +0   +0   +195514   -14   -109
   458752   3584000   +209331   -1   -7   +211903   -16   -125
   475136   3712000   +225728   -1   -7   +228292   -18   -140
   491520   3840000   +242126   +0   +0   +244674   -27   -210
   507904   3968000   +258523   +0   +0   +261058   -34   -265

Its talks for itself, polynomial second degree - two column on the right side, error in 19-bits count and error in micro-volt. Not too bad, about 15-bits linearity, but now we know that switches are not the same. MAX4544, probably can do better than 18-bits, at this time I can't be sure that my ADC is not the one who is not linear.

[Andreas]

Hello,

thanks for the comparison.
I made a diagram out of it (since a picture tells more than 100 lines of tables

If you look closer then you see that the 5717 is not repeatable in both measurements (at the highest output voltage).
I fear that for more repeatable results you will to have to replace the breadbord (many undefined contacts) by at least a (soldered) perfboard.

with best regards

Andreas

[MasterT]

Hello,

thanks for the comparison.
I made a diagram out of it (since a picture tells more than 100 lines of tables

If you look closer then you see that the 5717 is not repeatable in both measurements (at the highest output voltage).
I fear that for more repeatable results you will to have to replace the breadbord (many undefined contacts) by at least a (soldered) perfboard.

with best regards

Andreas

Yes, I know that results is reliable to no more than 16-bits, and max5717a is also only 16-bits. Simpy switching power on/off I observed that all circuits need 5-10 minutes just to settle down noisy data. DS for DAC doesn't specify "warm-up" timing, but it is  quite long, definitely not a few  seconds.
 I'm experimenting , replacing  switches and opa, so soldering is not an option. 
I repeat my tests with sn74hc4066, cd74hc4066,  max4542 and ts5v330c.  All of them produce jerky results, interesting that max4542 (dual NC spst) is noisy as the others, and it tells me that I can't easily compare results from different configuration - 1 pwm or 2 pwm with safe guard timing (1 clock on arduino 62.5 nsec). Obviously, 2  phase shifted pwm would create a random waves along breadboard, and even if its soldered, it'd be much more complicated to design a board, with 3-4 layers , separate grounds etc. SPDT break-before-make switches seems the best option to make good pwm dac w/o a headache.

[MasterT]

More updates. I find a worst test case scenario, CD4052, marking TI , but I get a pack of 10 from aliexpress long ago for a buck ot two, so could be anything except TI. Measuring Ron resistance  with multi-meter shows 300-560 OHm . And unbelievable, this simple integrator circuits prints

ADS1232.
   Linear: y = 0.999580 * x -261467.187500
   Linear: y = 0.995693 * x -257465.093750
   bin_C   uVolt   5717a   error   er_uV   pwmD   error   er_uV
   8192   64000   -253286   -7   -54   -249305   +3   +23
   24576   192000   -236908   -6   -46   -232992   +2   +15
   40960   320000   -220528   -3   -23   -216679   +2   +15
   57344   448000   -204148   +0   +0   -200369   +0   +0
   73728   576000   -187772   -1   -7   -184060   -5   -39
   90112   704000   -171392   +1   +7   -167744   -2   -15
   106496   832000   -155014   +1   +7   -151430   -2   -15
   122880   960000   -138637   +1   +7   -135111   +3   +23
   139264   1088000   -122259   +2   +15   -118799   +1   +7
   155648   1216000   -105881   +3   +23   -102486   +1   +7
   172032   1344000   -89504   +3   +23   -86169   +4   +31
   188416   1472000   -73127   +3   +23   -69859   +1   +7
   204800   1600000   -56749   +4   +31   -53549   -1   -7
   221184   1728000   -40372   +4   +31   -37238   -4   -31
   237568   1856000   -23996   +2   +15   -20922   -1   -7
   253952   1984000   -7619   +2   +15   -4606   +0   +0
   270336   2112000   +8757   +1   +7   +11707   +0   +0
   286720   2240000   +25134   +1   +7   +28019   -1   -7
   303104   2368000   +41510   +0   +0   +44330   -3   -23
   319488   2496000   +57887   +0   +0   +60643   -4   -31
   335872   2624000   +74263   +0   +0   +76958   -2   -15
   352256   2752000   +90640   +0   +0   +93272   -1   -7
   368640   2880000   +107017   -1   -7   +109587   +0   +0
   385024   3008000   +123394   -1   -7   +125900   +0   +0
   401408   3136000   +139771   -1   -7   +142215   +0   +0
   417792   3264000   +156147   -2   -15   +158531   +3   +23
   434176   3392000   +172526   +0   +0   +174844   +2   +15
   450560   3520000   +188904   +0   +0   +191157   +2   +15
   466944   3648000   +205279   -1   -7   +207470   +2   +15
   483328   3776000   +221657   +0   +0   +223784   +2   +15
   499712   3904000   +238032   -3   -23   +240092   -2   -15
   516096   4032000   +254411   -1   -7   +256408   +0   +0

 Switch, that was design 40-50 something years ago, stays in close match with modern bla-bla-bla extremely overpriced piece of .. silicon. Don't rush to spend $3+ on low R-on (max 4652 4OHm)  , test shows that cd4052 is much better!   
 

[RandallMcRee]

Thanks, again, MasterT.

I have spent some time this weekend looking at switches. One thing I notice is that the on/off times are pretty slow (especially with low charge injection switches).

Could you test the linearity at the lowest range (meaning narrowest pulses)? Seems like a switch like the hc4066 simply cannot be linear with pulses of less than 200nS or so.

But there are faster switches, like the ahc4066 (30ns rise) and I will also try the Hitachi TC7W66FU. Personally, I'm not trying to minimize cost, but, sure, who wants to spend more than necessary.

A different approach (I thank amspire for this) is to power a logic package from a precision +5v reference and use those gates to drive the PWM filter. Perhaps that approach would get better results especially in the lower range. Will need to compare with the switch approach.

Just fyi, one of my goals is to use an LTZ1000 reference. Obviously, this makes the native vref be 7.2v. So the main reason I am going to try the Hitachi switch is that you can power it from +12v and directly use vref from the LTZ (or a +10v reference). Using logic gates and also ahc4066 means stepping down 7.2 to 5v which is just another source of error. So, we'll see.

Attached: proposed filter.

[amspire]

There is a range of very high speed cmos chips from Potato Semicinductor

http://www.ibselectronics.biz/active/potato-semiconductor.htm

The PO74G00A for example has a 0.8ns rise and fall time and a 1.5ns high and low propagation delay. They are only 3.6V chips but they accept a 5.5V logic drive. The actual absolute maximum operating voltage is 4.6V.

I just haven't seen anyone sell them so I do not know the price.

Edit: The PotatosSemi parts are available from an eBay store:

http://stores.ebay.com/potatosemi_W0QQsspagenameZMEQ3aFQ3aSTQQtZkm

$3 for a basic logic chip.

I just ordered a few of these 8 pin clock buffer chips: http://www.potatosemi.com/potatosemiweb/datasheet/PO74G38072A.pdf
https://www.ebay.com/itm/38074-GHz-CMOS-Output-Clock-buffer-IC-8pin-SOIC-QTY-1-/330378214526

The chips come with extra Vcc and GND pins that probably helps reduce errors.

[RandallMcRee]

Folks, I have looked into the Keithley 263 (Thanks Alex Nikitin). It uses a gate driver and two 2N7000 mosfets. These have 10ns rise/fall specs. So perhaps Keithley found "normal" analog switches not up to the task?

[amspire]

One of the things makes sense with using a logic IC powered from the reference voltage is that the PWM needs buffering anyway. The only filtering I needed on the PWMs in that earlier post was simple multistage RC filters which behave pretty close to ideal.

Since you need a buffer, you can use a low-offset or a auto-zero opamp along with something like the Linear Technology LT5400A-1/LT5400B-1 4x 10K resistor array to boost the voltage by a factor of 3 or 4 with a 0.01%/0.025% accuracy, 0.2ppm/C coefficient and 2ppm/2000hours long term stability.

If you can live with the "B" grade array, it is almost a third the cost.

[MasterT]

Could you test the linearity at the lowest range (meaning narrowest pulses)? Seems like a switch like the hc4066 simply cannot be linear with pulses of less than 200nS or so.

 You can calculate pulse width out of arduino's printout, it's in bin_C , all it takes is convert 19bits back to 12bits and multiply 62.5 nanoseconds arduino clock cycles. So 8192 in the first line corresponds to 8192 /128 *0.0625 = 4 useconds, and 516096 to 252 usec pulse width PWM. You are asking below 200 nsec, in arduino cycles it's only 3 clock periods.
Here is the measurement from the beginning. CD4052 chip, is the slowest one in my collection. Sure it's not linear, I don't think there is an issue. Arduino could generate not exactly 4096 clock cycles, but 4196, so cutting 100 from the start (signal conditioning after the dac) we can easily solve a problem with offset error

[Kleinstein]

Folks, I have looked into the Keithley 263 (Thanks Alex Nikitin). It uses a gate driver and two 2N7000 mosfets. These have 10ns rise/fall specs. So perhaps Keithley found "normal" analog switches not up to the task?

The Keithley design is rather old. In the early days the choice of CMOS switches was not that large and not that many low R_on switches. In many respect the R_on could be the more important factor than the switching speed. Speed comes in mainly indirectly, as higher speed usually also means lower jitter. A difference in R_on is mainly what effects linearity.

The CD4052 is not only lower speed but also higher R_on.

[MisterDiodes]

RandallM:  Just out of curiosity - you want to build a 12-bit DAC that is 24-bit accurate using PWM... Just exactly how do you plan on measuring a physical circuit to verify proper operation?  Measuring to better than 20 bits (1ppm) <absolute value> is not easy and requires something equivalent to perhaps several 732-grade Vrefs. if you're after long time frame stability - if that's what you need.  Measuring <ratios> at higher than 20 bits is a challenge too - be careful of the equipment you're using to measure.

Or is this just a thought exercise for fun?

You do realize you can buy 16 / 18 bit DAC's off the shelf for < $5 that will guarantee you 12-bit accuracy without doing anything else (and give you some "bit room" to caress a compensation curve)...of course diffused resistors will add a bit of noise - but what is the budget for this device you're planning (in dollars - or are you going typical EEVblog style => cheap as possible??) and what is the allowed noise budget  and long term drift rate???

Coming up with answers to those questions first will help fence in the design later on.

PWM methods can work to a point - but just remember getting rid of noise is sometimes harder than not generating noise in the first place ( Don't forget the impact of noise in your power rails and EMI problems with fast edges).  The switches and noise injection / Ron are always a weak link in the chain here as you are finding out.  You also might look at the higher end JFET switch designs that will work well at 7~15VDC ranges with very low charge injection.  They won't be cheap, but precision doesn't come free either.

[RandallMcRee]

RandallM:  Just out of curiosity - you want to build a 12-bit DAC that is 24-bit accurate using PWM... Just exactly how do you plan on measuring a physical circuit to verify proper operation?  Measuring to better than 20 bits (1ppm) <absolute value> is not easy and requires something equivalent to perhaps several 732-grade Vrefs. if you're after long time frame stability - if that's what you need.  Measuring <ratios> at higher than 20 bits is a challenge too - be careful of the equipment you're using to measure.

Or is this just a thought exercise for fun?

It is true that I do not have the equipment needed to verify performance. But, I do intend to build a PWM and, hopefully, over time, with others help, can do some verification. The whole idea (in my mind, even if not clear from goals) is to create something that is 24-bit linear by design.  If the particular PWM design does not meet its goals then again, hopefully, the design can be updated so that it does. I do plan on having a 16-bit DAC on hand to compare directly with the PWM. Its an AD5546CRUZ.

This is for fun, but its not solely a thought exercise.

[amspire]

RandallM:  Just out of curiosity - you want to build a 12-bit DAC that is 24-bit accurate using PWM... Just exactly how do you plan on measuring a physical circuit to verify proper operation?

It depends on the reason for asking for the 24-bit linearity. If the reason was to have voltage increments for the 12 bit D/A that were uniform in size to within 0.1%, then that is something PWM does much better then a 12 bit D/A. So if 0xFFF is set to better than 0.1% accuracy, then 0x001 is also 0.1% accurate. For a 12 bit D/A, 0x001 would probably have around a 50% accuracy.

Also a PWM can be very cheap. I have used PWM where I want very precise adjustability (ie high resolution but not high accuracy) without the cost of 24 to 32 bit D/A chips. One of the evils in going from analog to digital is you often go from a linear stepless adjustment to discrete steps. For example, modern power supplies that can often only manage 1mV steps compared to older analog supplies with a multi-turn FINE voltage control that goes well below 1mV in resolution.

[MisterDiodes]

RandallM:

Any thoughts on what your goal noise density at the output? At what freq??  And at what dollar budget are you shooting for?

Just bear in mind - at one low end of the spectrum you've got a cheap & simple DAC chip that doesn't contribute switching noise but not as accurate as you'd like - at the extreme other end, for true 23~24 bit accuracy you've got this for a target accuracy spec inspiration @ dollar budget cost:

https://www.ietlabs.com/kvd-700.html

...A true DAC that works to DC and includes a built-in 7-digit non volatile memory.  Too bad it uses foil resistors, that makes it slightly more noisy than PWW, but you can't have everything for USD $30,000 

EDIT: Fluke's USA List Price on a 720a is currently USD$ 46,255.  So if you consider that an approximate 24-bit accurate DAC - that gives you an idea that a PWM method budget might be somewhere below that...  That's a pretty big ballpark range.

I would suggest this:  I would look at a PWM methods where you try for 16 / 18 / 20 bits true accuracy first, on real circuits, which is more in the realm of practical.  You will find out where theory ends and reality begins...  And that will guide you on to what's required for tighter accuracy.

At around 20~21 bits - You'll find that's about where the never ending switch & clock stability problems become more apparent, and you'll also see that pesky switch TC and noise effects creep in.  Beyond that you'll usually find a steep wall where it's harder (and much more expensive) to maintain real accuracy.  Resolution is usually meaningless without accuracy for real metrology applications.

If you're going for "cheap" - yes, that's always nice but generally you get what exactly you pay for.  Sometimes that's plenty enough depending on what you really need.

You'll also find out along the way that the often-quoted EDN design idea for a 32-bit DAC was a complete fantasy - and you'll learn why.

Have fun!!

[RandallMcRee]

I modified post #1 with a proposed schematic. Its a standalone PWM although I assume an arduino or similar loads a counter with some desired value.

The kicad schematic is on github at: https://github.com/RMcRee/12-bit-linear-pwm

I went with the amspire idea of using a 74HC to directly drive the filter. After examining and buying many analog switches I thought the simplicity of that idea was too tempting not to try.

Posting png here so you don't have to flip back to the start...

[amspire]

You have gone for 74FCT and 74F chips - I assume for their speed. The 74F chips in particular use a lot of power and could add a lot noise into the board.

You can eliminate the need for super-fast IC speeds and improve timing accuracy by just adding one synchronous latch before the 74HC74. The latch resyncs the transitions to the clock edges.

The 74FCT163s clock on a rising edge. Just set the output latch to clock on the falling edge. You only need enough speed then to reach the correct state in 50 ns instead of trying to find sub 10ns speeds.
Edit: My mistake, I see you are using the output 74HC74 also as a latch. There could be some feedthrough from the clock and the non latched data inputs to this output IC. I usually have the latch and output IC separate so the output IC only sees a very precisely clocked input and nothing else.

If the output is latched, do you need 74F chips?

[RandallMcRee]

Yes, the 74F series is scary around precision stuff. I got there like this:
10Mhz is 100nS between clock transitions (budget).
An 74HC74 latch needs 18nS of setup time (82 nS left)
The fct163 has prop. delay of 12nS (so 70ns remaining).
The simple three cascaded 74hc85 requires three propagation delays, but one prop is 50nS worst case (over budget). The 74F85 gets those three delays in 14+9+9=32nS.

Hmm, what about using the hc688 and the A=B output?
hc688 prop delay is 51 nS. Need NAND gate (can't use En to cascade!) so that is another 9nS, so 60 nS. So, I think that is just possible. I'll give that a try....

Thanks!

[Kleinstein]

What is the purpose of the discrete logic PWM generation ? The µCs are supposed to be about as fast as 74HC logic. If you have some doubt on the clock stability of the µC (e.g. µC with internal PLL), one can add an extra synchronizing flip-flop after the µC.

When it comes to linearity, one has the think about the output resistance and the loading to the switches part. The filter shown below would be a load that depends on frequency / PWM setting.

At the sub-ppm end also resistors may not be as linear as needed. Self heating alone can make the resistors nonlinear. So the filter shown may not be such a good solution as it uses several resistors that need to be linear.

[amspire]

What is the purpose of the discrete logic PWM generation ? The µCs are supposed to be about as fast as 74HC logic. If you have some doubt on the clock stability of the µC (e.g. µC with internal PLL), one can add an extra synchronizing flip-flop after the µC.

Randall knows that. He just wanted to do it using discrete logic.

I did some tests on jitter with an atmega324P and it is very good. Forgotten the numbers but it is sub-nanoseconds as long as you use the high power clock. The low power clock is rubbish.
So none of that was ever an issue here. I guess Randall liked something that just worked without any programming.

When it comes to linearity, one has the think about the output resistance and the loading to the switches part. The filter shown below would be a load that depends on frequency / PWM setting.

At the sub-ppm end also resistors may not be as linear as needed. Self heating alone can make the resistors nonlinear. So the filter shown may not be such a good solution as it uses several resistors that need to be linear.

You are talking about resistance changes due to self-heating over 400us. Any resistance change over a longer period doesn't matter. I doubt the change over 400us is very much. I have played with metal film with very high precision and you could see drifts such as 10ppm/second on applying a 5V load. Say it is 100ppm/second. That would equate to 0.04ppm over 400us. That is down in the noise level.

As far as the filter is concerned, the PWM frequency is constant - at 2.44KHz I guess. These third order Salen Key filters work pretty well here as the worst of the HF noise is handled by the initial RC filters. By the time the signal reaches the opamp, the HF components are very attenuated so the opamp can usually handle it very well. He could get down to 24 bit resolution with multi RC stages without any active filter but you are talking about settling times of about a second. Randall wanted it 10 times faster.

The cmos output is used mostly at 0-4mv or 4.996 - 5V. Over such a small variation, the channel resistance changes very little. It also doesn't matter if the channel resistance changes with temperature if both the sink and source channels increase equally with temperature.

The main issue is the difference in source and sink channel resistance. It will have an effect. If it is 10 ohms, then with the current parts chosen, you can get a one 12 bit count error midscale. If an extra RC stage was added with a 100K resistor at the start, this might be reducible by a factor of 4.

Again I think Randall knows this. I think the idea is to build something - then he can play with it. the Mark I design will work pretty well and if he is lucky, it may even work better then expected. But he has hundreds or even thousand of different cmos devices he can look to as the PWM switch. It can just be added after the 74HC74. The PWM switch is the critical part. I think Randall didn't want to start with an expensive solution that might not work any better.

[BravoV]

Subscribed.

[RandallMcRee]

Thanks, Amspire. Yes, you represented the project goals well.

1) The counter stuff is to make it stand-alone. Presumably, anyone who looks at the project can say to themselves "oh hey I don't need all of that counter stuff". But I envisioned this sitting, alone and lonely, in a lab happily generating a precision voltage while the microcontroller is being flogged by an update. Also, you get to use your ovenized, weaponized, cesium-locked, rubidium-checked 10Mhz clock. It's lonely too, just sitting on the shelf.

2) This is the first time I have ever heard that a filter might need low TCR resistors. I hope not. But if so, that would actually be a cool learning experience. Not just for me, I suspect. It seems like the 9.1k/Ron ratio is the important quantity. We could also simply scale that resistor up, that's easy. Noise increases so there is a tradeoff, there. But the ratio is ~ 1000:1 I think.

3)  Yes, I actually bought many analog switches but then I could not see any benefit in complicating the circuit. So this will establish a baseline. If there is a benefit we should be able to quantify it. I could not find an analog switch that met *all* of these criteria: ron<2ohms, Ton < 10nS, control levels hc compatible, source-drain voltages 12v or more, ideally +-15v.

Thanks

[ch_scr]

Regarding the ATMega pwm stability i have a story to share, a while ago i tried to do low frequency sine wave generation via dds & pwm on an ATMega8. 12 Bit pwm, max frequency around 10-20 Hz. Sinewave from a lookup table, as many points as i could fit inside the Flash. I used the Scopes FFT to check purity after the filter, and sure enough found my pwm switching frequency there, very surprising for me together with what looked like sidebands. After some trying, i switched of my dds loop and had only the PWM going on a fixed value; sidebands gone. Got the DDS going again, sidebands where back. I found a discussion online hinting that updating the value of the pwm output value (comperator register) is done before the beginning of a new counting cycle (the value is loaded from the shadow register to the actual comparing register). As this takes time, the PWM cycle time would be slightly longer after an "update event".

[RandallMcRee]

Version 2, using HC688 and JK flip flop.

[MisterDiodes]

No. Not close to an accurate DAC if I'm looking at your schematic correctly.

Learn the limitation of 74AC logic family on your PWM:  For a PWM DAC to be accurate, you have to accurately PWM  switch between Vref and 0 volts (usually - and I think that's what you are assuming might magically happen here). On your circuit you're switching between some unknown high voltage of around VRef-0.25V to VRef-.1V typical (depends on manufacturer, temperature, load etc.) and on low side you're have an unknown voltage somewhere between 0 to 0.25V.  With a strong TC by the way.

Notice the Ti datasheet will typically only list the MIN and MAX Vol and Voh...that's not what a real CMOS 74xx output does when you have a non-zero load impedance.  Typically you never reach true zero volts or true Vref output voltage swing limits.

In other words, logic chips ain't real analog switches, and normally they are never used that way - and that's why.

Also look at your output filter.  That's why I was asking you about noise budget / and low TC.  It's a challenge to design op-amp filters that maintain very high DC accuracy at low enough noise to even reach true 18/20 bits, let alone 24 bits over even a small temperature range.  The resistors and caps specs aren't trivial, and look at the TC of your amps.

I suggest you go back and look at your analog switch requirements you listed and do a bit of research.  Learn why those specs you listed are hard goals to reach simultaneously in a solid-state switch.  You want fast switching, but high dv/dt on the gate means higher charge injection.  You want low RdsOn, but that isn't necessarily fast or low charge injection.  If you have low charge injection you'll tend to have higher RdsOn. Learn why that tends to be the case.  This is a great time to learn the physics involved and learn how to read "between the lines" on a datasheet.

Hint: Investigate how you drive a good Jfet switch with another one....

These are just some of the reasons why there are limits on the true accuracy of various PWM techniques for DAC applications.

Have fun!

[amspire]

No. Not close to an accurate DAC if I'm looking at your schematic correctly.

Learn the limitation of 74AC logic family on your PWM:  For a PWM DAC to be accurate, you have to accurately PWM  switch between Vref and 0 volts (usually - and I think that's what you are assuming might magically happen here). On your circuit you're switching between some unknown high voltage of around VRef-0.25V to VRef-.1V typical (depends on manufacturer, temperature, load etc.) and on low side you're have an unknown voltage somewhere between 0 to 0.25V.  With a strong TC by the way.

Notice the Ti datasheet will typically only list the MIN and MAX Vol and Voh...that's not what a real CMOS 74xx output does when you have a non-zero load impedance.  Typically you never reach true zero volts or true Vref output voltage swing limits.

In other words, logic chips ain't real analog switches, and normally they are never used that way - and that's why.

Also look at your output filter.  That's why I was asking you about noise budget / and low TC.  It's a challenge to design op-amp filters that maintain very high DC accuracy at low enough noise to even reach true 18/20 bits, let alone 24 bits over even a small temperature range.  The resistors and caps specs aren't trivial, and look at the TC of your amps.

I suggest you go back and look at your analog switch requirements you listed and do a bit of research.  Learn why those specs you listed are hard goals to reach simultaneously in a solid-state switch.  You want fast switching, but high dv/dt on the gate means higher charge injection.  You want low RdsOn, but that isn't necessarily fast or low charge injection.  If you have low charge injection you'll tend to have higher RdsOn. Learn why that tends to be the case.  This is a great time to learn the physics involved and learn how to read "between the lines" on a datasheet.

Hint: Investigate how you drive a good Jfet switch with another one....

These are just some of the reasons why there are limits on the true accuracy of various PWM techniques for DAC applications.

Have fun!

And yet, here is the results from a test I did years ago using a 74HC11 PWM output (from memory):


Strange?

You are a little right in that I have already pointed out using the flip flop as the switch is a bad idea. The problem is it has a 10MHz clock coming in. This means the chip is consuming a signifigant current and so you will get errors on the outputs. The PWM output will not be clean for sure. You need a device with one switched logic PWM input and one PWM output in use. No other input should be changing and no other output should be used.

As long as you choose a simple logic chip that is only doing one job - switching one output, physics ends up winning over datasheets. The reason is simple. If the chip is drawing no current and a ON mosfet is connected to 0v or Vref, there is no reason, other then the mosfet's resistance for voltage drops. The mosfet's resistance is a factor, but I covered that in my last post.

You just don't get unexplained offsets of 0.25v. Those are specs that include the fact that the rest of the chip may be under worse case conditions. The mosfets do not stop being mosfets as the voltage across them approaches zero. You seem to be suggesting that a mosfet output pulling high actually starts sinking voltage to prevent the output from reaching VRef.

Have you ever actually seen this strange effect?

The reason I didn't press the point on the '74 as a PWM output was that is is obvious Randall wants to build this so he had something to start testing and developing, and so the critical thing was to have a circuit that worked up to the digital PWM output. Once he has that, he can experiment. The flip flop is needed anyway, but he will need to follow it with another chip - could be a 74HC or it could be a cmos MOSFET driver chip or anything he wants to try.

The opamps offsets could be an issue and I never bothered to even check Randall's choice there. I think there are times where it is better just to try something.

Back to the image of linearity tests above. The results are crazier then you think. That is the results of a breadboard test using the 74HC11 PWM output chip and a LM324 opamp as a x3 buffer!

I hate to think what you will say when you pull out the LM324 datasheets! There are times, especially when doing hobbyist work, that it is better to forget the datasheets and just test it for yourself. Randall's circuit is a fabulous starting point for a lot of experimenting.

If he cracks the magic combination of PWM chip + filter which is not impossible - he will be laughing.

[RandallMcRee]

Thanks for reading. As I said before, I do want to establish a baseline. One minor point is that the ac109 Q output is driving a 9.1k resistor so that should not be too much current, methinks.

So aware, of that first point.

What I'm most unclear on is the point about the filter.  You say:

Also look at your output filter.  That's why I was asking you about noise budget / and low TC.  It's a challenge to design op-amp filters that maintain very high DC accuracy at low enough noise to even reach true 18/20 bits, let alone 24 bits over even a small temperature range.  The resistors and caps specs aren't trivial, and look at the TC of your amps.

Can you point me to some references on this? How would I calculate the noise for my proposed filter? I had thought that the LT6018 would be acceptable, providing good GBW which a LPF needs along with 0.5?V/°C Vos drift. Vos is low, but I think we all decided, collectively, that absolute values are not as important as stability over time, temperature.

http://cds.linear.com/docs/en/datasheet/6018fa.pdf

Not clear (to me) that a chopper amp is suitable for a PWM LPF filter given the low slew rate, etc.

Yep, here to learn.

Just saw Amspire's post. Amspire can you draw up a quick schematic for what you are thinking? Basically have PWM filter driver be after the FF (which is now 'normal' logic) and be an HC gate or AHC or? Does it matter?

[amspire]

Just saw Amspire's post. Amspire can you draw up a quick schematic for what you are thinking? Basically have PWM filter driver be after the FF (which is now 'normal' logic) and be an HC gate or AHC or? Does it matter?

I think you are doing a great job up to the output flip flop. Power that from the logic supply.

Plan you layout so you can try different simple logic chips or analog switches as your PWM output. Perhaps initially you make the whole PWM section a different board and initially just do it using the daed bug approach as used by the late great Jim Williams.

https://www.eeweb.com/profile/eric-holland/articles/remembering-jim-williams-dead-bug-style

The thing about the dead bug builds is that the performance is superb - about as good as you can get. You can just try it without designing boards. All you need is blank PCB and the parts.

I do not know the best IC to try for the PWM so try a number of them. What you are looking for is a logic IC that has very little quiescent current, that has high and that has low channel resistances that match as closely as possible. You can test channel resistance with a 10K resistors as a load. Just measure the output to rail voltage. You will get resistance on the output switches, but you want matching resistances. Put you finger on the IC to see if how the resistances track as the IC heats. You will never get something with zero resistance, but the mosfet resistance is not the problem - it is the difference between the high/low channel resistance that is the problem.

If you could find a simple logic chip with an output like an atmega328P arduino chip is would be great. They have about 20 ohms resistance, and they match within a few ohms. Not perfect for you, but pretty good.

I have ordered a few Potato Semiconductors PO74G38074 chips from eBay just to try out. These are 1.5ns clock buffer chips. Extra supply pins which is great. With the 4 output connected together, they can drive at least 50mA. Absolutely no idea of the resistance. The datasheet says the absolute maximum voltage is 4.6V, but I think I will test how they work at 5V for the fun of it. In fact, I will add a series resistor to the supply and see how high the supply can go before the quiescent current goes up, or the IC breaks down non-destructively . It could turn out these chips cause a nasty transient on Vref every time they switch. The quiescent current of these chips may prove to be an issue.

If you have a multimeter with a >>1G input impedance rather then the 10M of ordinary DVMs, you do not have to worry about the filter at the start. Just use a 3 stage RC filter with a time constant of around 1 second. Pick good low leakage caps - no electrolytics or high value ceramic caps. (If the ceramic caps are not NPO/COG, the capacitance often changes with voltage).

[MisterDiodes]

Thanks for reading. As I said before, I do want to establish a baseline. One minor point is that the ac109 Q output is driving a 9.1k resistor so that should not be too much current, methinks.


Vos is low, but I think we all decided, collectively, that absolute values are not as important as stability over time, temperature.

Not clear (to me) that a chopper amp is suitable for a PWM LPF filter given the low slew rate, etc.

Yep, here to learn.

OK, then learn:

The voltage drop on 74AC outputs will ruin your attempted high accuracy in a hurry - every uA will show up as voltage drop (down from Vref and up from gnd), and last I checked you're pulling 549 of those at a 5V Vref into a 9.1k load.  That is very significant if you're trying to maintain DAC accuracy - which is the whole point of this exercise, I thought.  The specs for output 74AC Voh and Vol are typically at a few uA.  These are NOT analog switches, and they are never designed for that.     

If your filter amp is drifting measurably and significantly per deg C relative to your goal accuracy - and that's going to make your acceptable operating temp range very small.  When your going for 24 bits - which is in your first post - think about what noise & drift level you're going to have to achieve on the output if these is going to work over say even 10 deg C.

That is where you're going to have to measure a real physical circuit to find what reality has in store for you.

Go ahead and have fun learning where the limits are...Datasheets and specs to the wind, who need's em?

[MisterDiodes]

I know this approaches a pesky datasheet full of facts that get in the way, but for anyone who doesn't understand the 74AC (FACT Logic) family - this might be useful:

http://www.onsemi.com/pub/Collateral/AND8277-D.PDF

Notice at even -50uA the voltage drop on an output pin Voh is already 10mV down (typical !!!) and can be up to 100mV down from the Randall's Vref on a perfectly normal part.  At +50uA Vol has a voltage rise anywhere 1mV to .1V.

And Randall is running ~549uA current, or over 10X as much.  That's why he could see well over a .1V drop off the planned power rail Vref and Gnd swing points.   Or maybe not.  Depending on what part he got he could see a PWM swing level not of Vref to zero, but typically Vref - 11mV or down to less than Vref - 200mV.

Relative to the accuracy goals of even a modest DAC these errors are pretty large.  The PWM calcs are only really accurate when you PWM switch between two KNOWN voltage points.

"But MisterDiodes!  The part datasheet says it can source or sink 24mA!!  What happened?"  That's because at 24mA your voltage drop off the rails is now in the ~.75V (high) ~.45 V range (low).   The output drivers are a bit more complex than a simple dual FET pair.

Again - not to discourage RM, just showing the "why" and "why not" of trying to use a logic gate as an analog switch.

Carry on having fun!

[amspire]

D.PDF]http://www.onsemi.com/pub/Collateral/AND8277-D.PDF[/url]
Notice at even -50uA the voltage drop on an output pin Voh is already 10mV down (typical !!!) and can be up to 100mV down from the Randall's Vref on a perfectly normal part.  At +50uA Vol has a voltage rise anywhere 1mV to .1V.

And Randall is running ~549uA current, or over 10X as much.  That's why he could see well over a .1V drop off the planned power rail Vref and Gnd swing points.   Or maybe not.  Depending on what part he got he could see a PWM swing level not of Vref to zero, but typically Vref - 11mV or down to less than Vref - 200mV.

We know mosfets have resistance. For PWM, resistance in the mosfets do not matter - it is just the difference between the source and sink mosfet resistance. It has all been discussed before - I did the calculations. It would be nice to find a chip with a lower mosfet resistance but this is to get started - and as you say learn.

This V1 design will not be 24 bit accurate, but the logic part is fine. It gives a platform to test analog switch and filter options. He might end up with discrete FETs.

If you go back a few posts, I demonstrated the reality of PWM linearity using a 74HC11 as the PWM switch and a LM324 as a 3x buffer. It is better then you would guess. The biggest error was 0.003%. Is that the numbers you expect by looking at the data sheets?

[David Hess]

The datasheet numbers reflect automatic testing limitations.  With the specified load, the part is tested for the minimum and maximum output voltages listed.  Those number represent a performance guarantee applicable to logic applications but only exist for testing purposes.

As far as analog, using an AC or other CMOS family gate as a precision modulator works fine and all of the usual characteristics like on resistance and leakage apply.  50 microamps into about 8 ohms (5 volt Vcc and sinking current, sourcing current the resistance is about 12 ohms from the lower performance p-channel MOSFET) yields an error of 400 microvolts which is far from the 100 millivolts used for testing.  One complication is that the reference voltages, Vcc and ground in this case, also determine the switching threshold voltages and cross conduction between Vcc and ground during switching is considerable so demands for low impedance and fast recovery of the reference are greatly increased over using analog switches which have no cross conduction when break-before-make operation is used.

Run a simple test yourself to find out.  Setup a gate with a low output and measure the voltage between ground and the gate output with various high value pull-up resistors.  10 megohms will yield 500 nanoamps and a voltage difference of about 4 microvolts.  You do not need a high impedance voltage to make this measurement because the output resistance is completely dominated by the 8 ohm channel resistance.

[MisterDiodes]

Ampsire:  .003% error is 30ppm...maybe 14~15 bits or about 300X more  error than what Randall is asking about in first post.  This is the metrology section, and he's asking for something in the ~0.1ppm error range, or close to it.  He won't really get there but it's good to know why an excellent analog switch is important (weak) link in the chain for PWM techniques.

David:  Yes, I agree that a logic gate can be used for analog switch to make a mediocre PWM DAC.  True.  And ON Semi tests their 'AC devices to 1mV voltage drops, not 100mV.  But that's not what Randall is asking about - he wants to make a good DAC.  And he's not running 500nA load, he's got a ~550uA load (max).  At 24 bits goal accuracy every uV error matters...a lot...and there are plenty of uV errors to be had.

The load seen by the upper and lower switches of the gate will also change as the average voltage on the first RC filter cap changes & remember those FET's aren't matched at all.  And for a variety of other tweaks that have to be built into a logic gate to make it work AS A LOGIC GATE (not a precision analog switch) and at controlled power (latchup protection, slew rate control if used, shoot-thru protection, static protection, multiple gates on one substrate problems, etc. etc.).  All of those manufacturer-specific features tend to diminish the usability of a logic gate for precision analog switch applications, and that's why we tend to use good discrete fets for higher precision switches - That way you have better control of the variables.

For instance: I'm looking at a 74AC14 right now with a 5V VDD and a 10k pull down, and it ain't no 8 ohms channel resistance on the upper - it's more like 26 ohms apparent for a Vdrop of 13mV at ~500uA current.  Stuff like this is a big deal if you're building an accurate DAC.  Even at no load (or the load of my Fluke 87 meter) there is a Vdrop off the upper or lower rails of a mV or two - that's going to limit the range of the DAC near 0% or 100% duty cycle.

Carry on Randall. Try the 74AC109 as a precision switch and see how it works.  It's always interesting to see what happens when your PWM runs at 0% and near 100% PWM...and in your case I would guess you might see some better  linearity performance around 70% to 80% zone.

[Kleinstein]

Those logic gates are not that bad to generate precise switching towards the supply. Some old meter (AFAIR Keithley 196 or 7) use CMOS 4000 series in there ADC for switching and even the 3458 uses just an 74HC14 for the last fine slopes.
One Problem however is that there is additional current at the supply from the logic / driver part - so the reference voltage buffer has to work harder. So dedicated switches or discrete FETs are likely a better choice and might also give better R_on matching.  As R_on is temperature dependent, external compensation of the different R_on is limited.

[MisterDiodes]

...Correct.  Remember that 3458a application doesn't need ultra high accuracy at that location.

Randall:  By all means try the cheap and simple way first.  That is a great learning experience to see where the limits are.

When you realize you need a higher precision PWM switch, start looking to Linear Systems' DMOS switches for much better performance and low charge injection, precision switching. 

http://linearsystems.com/lsdata/others/DMOSAnalogSwitchIntroduction.pdf

Another suggestion:  Start at your goal output specs and work your way BACKWARDS into your circuit to get an idea of where have critical performance needs...which at 24-bit accuracy will be just about everywhere.  For instance - if your op-amp has a 0.5uv/C° offset drift - well on a 5V max DAC output scale, 0.1ppm error (~24 bit) is about 0.5uV last I checked.  Which means the op-amp's Vos TC could possibly blow the error budget if the temperature changes a degree or two, roughly.  Likewise work backwards through your PWM filter and components to see what how they have to work without drift to contribute less than 0.5uV error to the output, then your precision analog switch and it's TC, clock freq / jitter tolerance etc.  All the way back to the power supply and its noise & error contribution.

This is why you want to start with a design goal of X bits accuracy of Y temp range with W noise density at Z Vref noise, T long term drift, J orbital position of Jupiter, and so on - whatever you need.  Add as many parameters as you like that are important to you.

You can even build up a spreadsheet and identify the most critical areas to work on, and then tackle each section one at a time.  Design / build / test / verify / tweak until you're at the goal for each section.  SPICE simulation becomes less and less effective at the higher accuracy ranges as reality takes over, especially when you start checking noise at over 20 bits.  As you move up each accuracy level it takes more and better equipment to verify also, plus you start keeping watch on uncertainty of measurement.  Even testing this device at around 20 bits accuracy is not easy.  At 24 bits you're probably left with going up against a Fluke 720a or similar, and still that might not be good enough.

Then you put it all together and see where reality STILL has a surprise for you here and there during final verification...but that's the basic design concept.

That's why I suggest a more modest goal first - see if you can hit 14-16 bits final PWM output accuracy first, then work up accuracy bits from there as you find the problem areas.  Each level of accuracy presents more challenges.

I'll shut up and leave you to it now....

[MisterDiodes]

Randall - I was reminded of this - If you don't have one of these around - these are actually pretty cool when you add a good 5V Vref to them, and are handy as a "stand in" tool for everything downstream of your PWM signal while you're tinkering on your high end DAC design:

http://www.linear.com/product/LTC2645

It's not 24 bit accurate, but a pretty good 12-bit PWM to voltage converter, and surprisingly quiet and stable IF you add a quiet and stable Vref.  Around 7 or 8 bucks.

Just an idea for something to compare to while you're playing with switches / filters etc.

HINT: It's a quad so try combining channels together for even higher resolution.  Knock yourself out!

More insight for what's in store for you in DN538 for building a PWM DAC.

[RandallMcRee]

Thanks, for your help. Here is another turn of the crank which shows using an LS SD5000 as the analog switch PWM drive.  I also evaluated the LP filter in AnalogDevice's filter wizard...or at least a close equivalent, I guess I should post that separately.

http://www.linearsystems.com/lsdata/datasheets/SD5000%205001%205400%205401%20QUAD%20N-CHANNEL%20LATERAL%20DMOS%20SWITCH%20ZENER%20PROTECTED.pdf

The circuit is just a combination of the multiplexer and SPST shown in the Linear System's app note.
In this circuit the input VREF could be +10V or LTZ1000 directly. Not constrained to +5V.

[RandallMcRee]

And here is the gate driver variant. This drives the PWM filter using an IXYS driver chip which has very low Ron and can supply ample current. Unlike using a logic gate we can also use +10V Vref, rather than +5V only.

http://www.ixysic.com/home/pdfs.nsf/www/IXD_609.pdf/$file/IXD_609.pdf

This is compatible, then, with the analog switch variant.

[RandallMcRee]

Here is a low-pass filter, optimized for noise, using Analog Filter Design Wizard. Using the ADA4522-2 seems fine, indeed, no opamp combination seems to achieve a 24 bit ENOB, but we do get to 22 bits.

ADA4522-2 is a chopper amp, so no 1/F noise.
http://www.analog.com/media/en/technical-documentation/data-sheets/ADA4522-1_4522-2_4522-4.pdf

Unfortunately, 3rd order filters require two stages in this designer. Does anyone know of a calculator that shows noise but allows a single opamp 3rd order stage implementation, such as I had initially?

[zhtoor]

maybe this would help:-

regards.

-zia

[Kleinstein]

The earlier filter type with a passive RC filter as a first stage was not that bad. Just the 2 nd order Sallen key LP filter can be tricky with very sharp edges coming through. The AD4522 is definitely a better choice than the high bias OP used before. Still the bias of the ADA4522 can become a problem even if only the bias drift would be the real problem.

I don't think the high power gate diver would be helpful, as it would cause too much supply trouble. If you want to go the gate driver way it would be more like small one like ICL7660 -  but like logic chips there is no separate pins for the output stage and the internal drivers. Chances are better with good analog CMOS switches (e.g. ADG633). For switching both the high and low side, it does not help to have monolithic MOSFETs like the SD5200, as the coupling through the substrate would be more of a problem.

Besides going very low switch resistance, there is also the option to reduce the voltage drop at the switches by using 2 switches, one for the first approximation delivering most of the current and a second to only do corrections but set the final voltage.

The LTC2645 is kind of a odd chip and not helpful at all. It converting PWM -> binary and than uses a conventional DAC.

[muvideo]

The design of such PWM DAC was recently submitted by adver on the forum radiokot.ru:
http://radiokot.ru/forum/viewtopic.php?p=3112844#p3112844
http://radiokot.ru/forum/viewtopic.php?p=3113890#p3113890 e.t.c.

Small Attiny25 with 8-bit PWM, software 3-order MASH, ADG419, OP177, 3-stage LP - that's all.

On PWM dithering and MASH...

Hello
I was trying to understand that design and I have a lot of questions,
hope will be a useful discussion in this thread.
Search for the topic on google returned a lot of Sigma-Delta stuff and MASH and most was
over my head, was unable to find a simple example for a PWM DAC.
What I understood so far is that in that design there is an 8-bit hardware PWM that is
dithered. The dithering is implemented in a way that keeps most of the frequency content
on higher part of the spectrum so keep the filtering easy.

I was trying to sketch a more detailed implementation, so let's start with basic dithering code first,
Let's say that I have a 8-bit hardware PWM running on a small uC, that alone will give about 40mV
of resolution on a 7 to 10V amplifier.
To increase the resolution the PWM should be dithered.

First order:
The simplest way would be to add 1 to the PWM register for some cycles so that the average value
will be somewhere between 2 PWM steps.
A more programmatic description would be : add 1 to PWM register F times every M cycles.
The resolution would be 1/M of PWM step. If PWM step for 8bit is 1/256, with
M=16 resolution would be 1/16 of 1/256 = 1/4096.
Example:
If we want 10V from 7V we need 2826/4096, hardware PWM register will be set to 176,
dithering will be F=10. Resolution 10V/4096=2.44mV.
So every 16 PWM updates we should have PWM=177 for 10 times and 176 for
remaining 6 times.

Is that correct?

In order to keep the filtering doable this PWM "modulation" should be done so to have
the least effect on low frequency content: so we should try to alternate PWM between
177 and 176 as frequently as possible.

A possible implementation in code would be:

Code: [Select]

/* DACvalue is the code I want to convert in analog voltage,
     it will be slit in 2 parts: an "integer" part that can go
     directly into the hardware PWM register and a "fractional"
     part F that will be obtained by dithering */

F=DACvalue % M;

at each PWM update:

sum += F+sum; /* where F is the fractional part of PWM value, can go form 0 to M-1*/
if(sum>=M)    /* where M is the dithering "depth" */
  {
  DV=1;
  sum=sum-M;
  }
else DV=0;

PWM = DACvalue/M+DV;


Is that correct?
Could it be defined first order MASH? Or what else?

Higher order:

Following this http://www.aholme.co.uk/Frac2/Mash.htm and from the first order code
I tried to implement dithering in C code for third order MASH (unoptimized but tried to
keep it readable)

Is that correct, will it work?
How big M will be in that design and in practice?
What is the advantage in having multiple stages?
Why 3 and not 4 or 2 stages?
What is a pratical limit on resolution for this modulation?

Thanks

Code: [Select]


int A1=0,A2=0,A3=0; // Adders input A
int B1=0,B2=0,B3=0; // Adders input B
int C1=0,C2=0,C3=0,C3_old=0; // Carry
int A_B1=0,A_B2=0,A_B3=0;    // Adders Output
int a=0,a_old=0,M=0,F=0,DN=0; // M: dither depth F: dither value between 0 and M-1, DN: dither output

F=DACvalue % M;

for each PWM cycle:

/* first stage */
B1 = A_B1; /* old value */
A1 = F;
A_B1 = A1+B1;
if(A_B1>=M)
{
  C1=1;
  A_B1=A_B1-M;
}
else C1=0;

/* second stage */
B2 = A_B2; /* old value */
A2 = A_B1;
A_B2 = A2+B2;
if(A_B2>=M)
{
  C2=1;
  A_B2=A_B2-M;
}
else C2=0;

/* third stage */
B3 = A_B3; /* old value */
A3 = A_B2;
A_B3 = A3+B3;
C3_old=C3;
if(A_B3>=M)
{
  C3=1;
  A_B3=A_B3-M;
}
else C3=0;

/* output */
a_old=a;
a=C2+C3-C3_old;
DN=C1+a-a_old;

PWM = DACvalue/M+DN /* update PWM register */


(edited, last line of both code pieces was wrong)

[amspire]

That code looks very complex for the task.

Take a look at this discussion with code.

https://www.eevblog.com/forum/projects/general-purpose-power-supply-design-7488/msg99807/#msg99807

I think this was where the discussion started.

We did it differently. We just kept a continuous running average and each PWM cycle, corrected for the cumulative errors from previous cycles.

The idea is to make the PWM interrupt as short as possible.

[muvideo]

That code looks very complex for the task.

Take a look at this discussion with code.

https://www.eevblog.com/forum/projects/general-purpose-power-supply-design-7488/msg99807/#msg99807

I think this was where the discussion started.

We did it differently. We just kept a continuous running average and each PWM cycle, corrected for the cumulative errors from previous cycles.

The idea is to make the PWM interrupt as short as possible.

isn't that implementation functionally the same as the first code snippet i wrote?
(your "value" in my case would be (PWM<<24)+F with M=2^24)
If I understand correctly also in your case, given a "value", your OCR2B register
will alternate between two adjacent codes.
An higher order modulator would have the pwm register vary between more
than two adjacent numbers.

Code: [Select]


OCR2B = (byte) (pwm_accum >> 24) ;   // Send the top byte of the PWM error accumulator to the PWM for the next cycle.
  pwm_accum = pwm_accum - (((unsigned long) OCR2B) << 24 ) ;  // Subtract the byte sent to the PWM from the top byte of the PWM error accumulator.
  pwm_accum = pwm_accum + value;   //Add the intended value for the output to the error from the last cycle


Code: [Select]

sum += F+sum; /* where F is the fractional part of PWM value, can go form 0 to M-1*/
if(sum>=M)    /* where M is the dithering "depth" */
  {
  DV=1;
  sum=sum-M;
  }
else DV=0;
PWM+=DV;


[MisterDiodes]

The LTC2645 is kind of a odd chip and not helpful at all. It converting PWM -> binary and than uses a conventional DAC.

That's the whole point!

You will notice in the spirit of my post (maybe I wasn't clear enough) that chip was never intended to be used in final design - just a suggestion for a handy & cheap tool to verify the PWM clocking is working about correct.  We keep a few on test boards for <testing> 8, 10 and 12 bit PWM signals.  That's all.  Of course that is very useful tool when <debugging> a PWM circuit.  Your expensive scope pwm measure function won't always be accurate if you're looking for a problem when the PWM signal steps between 1/4094 and 1/4095.  Ask me how I know...

Anyway...

Randall:
Now that you have a more known switching characteristic, now go back and look at your PWM filter design.  One way to look at it is you need around 140db or more reduction of the PWM clock freq (0.5uV/5V), and another way to look at it is you need WELL UNDER 0.5uV ripple AND overall error at the filter output - IF you want anything close to 24 bits accurate on final output and room for a bit of temperature span drifts.  Even on chopper amps, at 24 bits accuracy those very small TC offset drifts creep in.

You can use SPICE here as a first stab at filter design, and it is certainly useful, but keep in mind - LTSPICE doesn't know anything about how capacitors change value at bias, capacitor DA, resistor types in use  and how that affects 1/f noise, input current noise density effects and problems, etc. For chopper amps it doesn't know anything about how to look at switch charge injection, power rail noise injection or load dependent demod chop noise on the output.  All of these effects exist in real life and yes they are small - but you're target accuracy needs as small as possible.

I suggest you check your filter design at various PWM modulations at 0%,.01%, .1% 10%, 20%....90% 99%, 99.99% and 100% and see where your problem areas are.  Keep looking for that output ripple to be well below your target accuracy point, and make sure you've still got linearity.

Now that you get your filter with low ripple, step your PWM between .01% and 99.99% and see about how many seconds you're waiting for the filter output to stabilize.  This can be a problem area for PWM type DAC's.  Maybe it's not an issue for you.  Just something to look at.

Just a thought - something else down the line to be aware of:  Is this going to be in a box?  Are you going to bring the output to terminals?  At 24-bit accuracy you need sub uV errors on the output signal, and that means a careful look at any binding posts and every component placed downstream and around that output amp that can cause a thermal EMF error.  Study the Linear app notes and learn where you might need compensation joints in your traces to balance out thermal EMF's etc.  Just be on the lookout.

I would not deadbug circuits if you're going for over 18 bits accuracy.  From experience - just too many thermal issues at that point with wires flapping in the breeze..  That method can work for less fussy circuits.

Anytime you're out past 18~20 bits accuracy these types of problems pop up all the time, and these are the kinds of things no simulation handles completely.  You'll have to keep testing in the real world and keep tweaking.  Just a friendly head's up.

I'll really leave you to it now - Have fun!   

[doktor pyta]

Very interesting discussion.
Most of You know the DAC design by S. Woodward (first published in EDN) analyzed below:
http://www.openmusiclabs.com/learning/digital/pwm-dac/dual-pwm-circuits/index.html

[amspire]

That code looks very complex for the task.

Take a look at this discussion with code.

https://www.eevblog.com/forum/projects/general-purpose-power-supply-design-7488/msg99807/#msg99807

I think this was where the discussion started.

We did it differently. We just kept a continuous running average and each PWM cycle, corrected for the cumulative errors from previous cycles.

The idea is to make the PWM interrupt as short as possible.

isn't that implementation functionally the same as the first code snippet i wrote?
(your "value" in my case would be (PWM<<24)+F with M=2^24)
If I understand correctly also in your case, given a "value", your OCR2B register
will alternate between two adjacent codes.
An higher order modulator would have the pwm register vary between more
than two adjacent numbers.

Code: [Select]


OCR2B = (byte) (pwm_accum >> 24) ;   // Send the top byte of the PWM error accumulator to the PWM for the next cycle.
  pwm_accum = pwm_accum - (((unsigned long) OCR2B) << 24 ) ;  // Subtract the byte sent to the PWM from the top byte of the PWM error accumulator.
  pwm_accum = pwm_accum + value;   //Add the intended value for the output to the error from the last cycle


Code: [Select]

sum += F+sum; /* where F is the fractional part of PWM value, can go form 0 to M-1*/
if(sum>=M)    /* where M is the dithering "depth" */
  {
  DV=1;
  sum=sum-M;
  }
else DV=0;
PWM+=DV;


I was looking at the size of the larger piece of code. The shorter piece did not seem complete. I am not sure how the PWM register is set. All I could see was a PWM value that was incremented but never decremented.

Are you using the PWM registers, or are you just using the software to directly output the DV bit?

I gather that that article you mentioned uses harmonic cancellation at the expense of processor steps. It would be interesting to compare my solution that allows two PWM dacs to be running at cpu clock speed in a atmega328P with a 256 bit PWM size would compare in performance to a slower multistage piece of code but with easier filtering.

I could get a bit over 20 bit DAC resolution on each channel with a 1 second settling time using simple RC filters.

I can see the idea in the article working great in a FPGA where the whole logic can happen simultaneously in a pipeline. Thanks for pointing to it - very interesting.

[RandallMcRee]

Another interesting thing to consider (I don't think my project will incorporate this though) is to use a fully differential filter, whose inputs are Q and ~Q, i.e. the PWM and the inverse. If done, right that could help cancel both the ripple and switch charge injection. It seems like since the switches are balanced and the charge injection is dependent on switch geometry, the injected current will appear as a common-mode voltage on the two halves of the filter and be cancelled.

Seems like the Woodward 16-bit PWM does something similar.
Big caveat: I don't believe that FDAs exist that have the precision characteristics that are needed.

[MisterDiodes]

...Differentials can work, as long as you've got some somewhat close matching precision parts.  If the phase matching is off ever so slightly guess what happens to the output?  You've just arrived at Rippletown again.

[muvideo]

I was looking at the size of the larger piece of code. The shorter piece did not seem complete. I am not sure how the PWM register is set. All I could see was a PWM value that was incremented but never decremented.

Are you using the PWM registers, or are you just using the software to directly output the DV bit?

You are right, last line of the code I posted was wrong, I've edited it: DACvalue is the code I want to
convert in analog voltage...

Code: [Select]


F=DACvalue % M;

at each PWM update:

sum += F+sum; /* where F is the fractional part of PWM value, can go form 0 to M-1*/
if(sum>=M)    /* where M is the dithering "depth" */
  {
  DV=1;
  sum=sum-M;
  }
else DV=0;

PWM = DACvalue/M+DV;



I gather that that article you mentioned uses harmonic cancellation at the expense of processor steps. It would be interesting to compare my solution that allows two PWM dacs to be running at cpu clock speed in a atmega328P with a 256 bit PWM size would compare in performance to a slower multistage piece of code but with easier filtering.

I could get a bit over 20 bit DAC resolution on each channel with a 1 second settling time using simple RC filters.

I can see the idea in the article working great in a FPGA where the whole logic can happen simultaneously in a pipeline. Thanks for pointing to it - very interesting.

you are welcome,
the code I posted is just to understand the algorithm,
it should be rewritten and optimized for each application,
for example with PWM of 8bits and M of 16bits
the calculations will be pretty fast

[RandallMcRee]

At long last, I have a tested and working prototype of the PWM Dac. I tested only the IXDD609 gate driver and it works well.

I updated the first post of this series with the schematic and its also on github. Minor changes, only.
https://github.com/RMcRee/12-bit-linear-pwm

Attached is a photo of the prototype which is constructed using a ground plane and wire-wrap. Photo too big--posting separately.


Also attached is a pdf of some preliminary data.
Dac clock is 10Mhz OCXO from HP 5334B counter. Dac VRef input is 10volts from Fluke 731B.

The yellow columns are keithley 2015 measurements of selected codes. Note that, as expected the first code, 1, is 0.002743 as opposed to its theoretical value of 0.00244141. This is the only code that deviates much and is, I guess expected. The other columns calculate the DNL for these codes and show good agreement with ideal. Especially considering that measurements were taken by hand under strenuous conditions: arduino simply output codes sequentially and I wrote them down ASAP. Especially for the higher value codes the calculations are limited by the resolution of the meter.

Have been playing with it and repeatability and stability are excellent. Need to get my GPIB logging going again.

[RandallMcRee]

Photo of prototype....

[TiN]

Cool.
That amount of packages already begging for use of small CPLD instead 

[RandallMcRee]

Folks,
While working on this 12-bit PWM I saw a lot of ideas around the web for ways to make a high-resolution DAC by combining two PWMs. There is a thread sort of about this here:
https://www.eevblog.com/forum/projects/high-resolution-dual-pwm-dac-with-notch-filters/

The "problem" with virtually all of the ideas I have seen previously are that they rely on a resistor ratio to properly 'mix' the two PWMs in the correct amount.  The design in this thread allows a, different (obvious) way: for exactly one count out of every N (4096, here) mix in the other dac output via a switch. This is nice since when using a counter, the carry out signal of the counter+FF is exactly the switch control.

Advantages:
    No (evil) resistors are needed. You do need a fast analog switch, of course. Seems like the switch tphl vs tplh delta sets the accuracy;
    any sort of other DAC is fine, of any resolution. It could be PWM, R2R, etc.

Hopefully, the description is clear. I doubt that this is original but, like I said, have not seen this documented elsewhere. So here it is. Pretty sure it will work but I have not tested except in my head!

Randall

[Kleinstein]

For mixing in the fine DAC / PWM with an extra switch one would still need a resistor of some kind. It just is a resistor of same size as opposed to one 4096 times larger (or a comparable attenuator). So I don't see an advantage with using PWM type attenuation to set the ratio with resistors.

The scale for the fine corrections only needs to as accurate as the resolution used for accuracy of the fine part. If for example the overall DAC is something like 16 Bit coarse +  12 Bit fine the mixing resistors only have to be stable for 12 Bit accuracy. If the fine part is actually higher resolution and a little larger range this could be used to do the scaling by math and only a stable resistor ratio, but no accurate value is needed. In this case it might help to have a little extra HW to do the adjustment measurement internally. This could be comparing two settings to produce the nominal same value. It is a good self test and would reduce the requirements on the resistors from long time stable to shorter time scale (next "ACAL").

Higher resolution for the coarse part helps to keep the requirements for the fine part moderate. So it makes sense to use the higher PWM resolution modern µCs offer.

[RandallMcRee]

For mixing in the fine DAC / PWM with an extra switch one would still need a resistor of some kind. It just is a resistor of same size as opposed to one 4096 times larger (or a comparable attenuator). So I don't see an advantage with using PWM type attenuation to set the ratio with resistors.

No resistor necessary. I don't have a schematic at hand so let me just describe this:
The coarse PWM uses a 4053 type switch, say. It has an INH input (pin 6). Hook this up to ~ONE-COUNT. Your new SPST analog switch is just on/off and is controlled by ONE-COUNT signal. The SPST switch output can be directly wired to the 4053 output common since they are never on at the same time. (Of course, depending on the switches chosen you may get away with just one control signal since INH is negative logic and most switches are positive logic, but you get the idea).

Hope its clear, now.
Edit: fix bad signal name.

[Kleinstein]

I still don't fully understand the idea with the enable, but I am afraid this would involve rather short pulses and this will be a problem. To get good accuracy one has to avoid anything like a second switching in the time before the ref. buffer and similar have settled after any switching event. So there is kind of minimum length or likely a few µs, maybe 10's of µs if the buffer is not very fast. Using more switches also introduces switch resistance, which is even worse than true resistors as it usually has a high TC.

Anyway I don't see a problem with the scaling resistors - the ratio only needs to be as stable as the extra resolution added by the fine part. With enough overlap (so that the fine parts covers a little more than 2 coarse steps) one could even use some dithering, so that the resistor value would not be relevant over the long time average. Just a minute extra low frequency part with the amplitude of the resistor error: Over a longer scale the coarse part would produce the full resolution with dithering between 2 states. The fine part would correct to the best it can the resulting low frequency contribution from dithering.

[RandallMcRee]

Yes, fast switches will be necessary for accuracy. But switches seem to be getting faster and having lower Ron on a regular basis. So I think this technique will make a lot of sense in the future. At 100 nS it seems marginal today.

But the advantage here that you are not seeing is that the Ron of the switches looks into the low pass filter (we could/should for example set the initial R of the low pass filter to the value R-Ron). So, insofar as overall accuracy the switch Ron and TC as well only change filter characteristics--and not very much at that. Analog filter wizard shows how R and C changes affect overall filter and it is minor. Attached is 5% R/C analysis.

So, again, the PWM accuracy is principally set by the switch speed (not Ron) and frequency stability (orders of magnitude better than any resistor matching).

[Kleinstein]

The switches can still have an effect on filtered PWM accuracy. One effect it Ron matching for high and low signal. As R_on is rather temperature dependent, it is difficult to compensate with normal resistors.
The effect is not with changing the filter function (this effect is not relevant), but about a different resistance for the two levels - this would give a nonlinear contribution, as the current flowing during the H/L phase dependents on the average voltage with the normal low pass filter.

Another point is charge injection this will produce an extra spike. In first approximation this will be just a constant offset, but charge injection can depend on voltage / current and thus the level used. Another effect of charge injection it that the reference buffer will show some ringing / settling response. To a small part this can depend on the current flow, which would be bad. So the reference buffers are also important.

The resistor ratio for adding the fine part only needs to be stable to the contribution of the fine part. With sufficient resolution of the coarse part this will be only on the order of 0.01% - so the requires accuracy for resistor stability is not that high.  R_on is more like 0.1% of the filter resistor and thus R_on matching is more critical than this. I would consider a configuration with 12 Bit coarse and 12 Bit fine a poor choice. A better configuration would be more like 16 Bit coarse and 10-12 bits fine with 1-2 Bits of overlap. To avoid interaction between coarse and fine switching it might even be a good idea to use a conventional DAC for the fine part.