Author Topic: FET selection process for precision circuits?  (Read 9436 times)

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Offline VintageNut

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Re: FET selection process for precision circuits?
« Reply #25 on: May 02, 2018, 03:00:57 am »
I have been experimenting with JFETs this year making audio circuits. The obsolete Toshiba 2SK170 and 2SJ74 are the desired parts for preamps and for the input stage of power amplifiers. The noise spec is 0.95 nV per root hertz. Many new in-production JFETs have 10X to 100X worse noise.

The Toshiba JFETs are quite "drifty" over temperature. I think that any serious usage in calibrated test equipment probably has temperature drift compensation.

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Offline David Hess

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Re: FET selection process for precision circuits?
« Reply #26 on: May 02, 2018, 01:36:44 pm »
The Toshiba JFETs are quite "drifty" over temperature. I think that any serious usage in calibrated test equipment probably has temperature drift compensation.

In what sense are they "drifty"?

JFETs have a zero dVgs point at a specific drain current which may be too high for reasonable operation leaving using matched pairs in either a differential or stacked configuration.
 

Offline Cerebus

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Re: FET selection process for precision circuits?
« Reply #27 on: May 02, 2018, 02:33:12 pm »
JFETs have a zero dVgs point at a specific drain current which may be too high for reasonable operation leaving using matched pairs in either a differential or stacked configuration.

Odd terminology. Do you perhaps mean the point in the Vgs Id characteristic curve that exhibits a (close to) zero temperature coefficient? If so, that tends to be at around 20% of IDSS for most reasonable JFETs but some, with low Vgs(off), may push the zero tempco point closer to IDSS, as the zero tempco point occurs around Vgs(off) + 0.63V. The latter is certainly true of the xSK170 family with a Vgs(off) in the range -0.2 to -2 volts.
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Offline David Hess

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Re: FET selection process for precision circuits?
« Reply #28 on: May 03, 2018, 04:37:58 am »
JFETs have a zero dVgs point at a specific drain current which may be too high for reasonable operation leaving using matched pairs in either a differential or stacked configuration.

Odd terminology. Do you perhaps mean the point in the Vgs Id characteristic curve that exhibits a (close to) zero temperature coefficient? If so, that tends to be at around 20% of IDSS for most reasonable JFETs but some, with low Vgs(off), may push the zero tempco point closer to IDSS, as the zero tempco point occurs around Vgs(off) + 0.63V. The latter is certainly true of the xSK170 family with a Vgs(off) in the range -0.2 to -2 volts.

Yes, that is what I meant.

The problem is that if the drain current is too high at the point where the Vgs temperature cofficient is zero, then it limits the allowable drain voltage due to excessive power dissipation.  One way around this is to use a cascode at the drain if that is acceptable.  More commonly though a second matched JFET is used like I described.
 

Offline rhb

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Re: FET selection process for precision circuits?
« Reply #29 on: May 05, 2018, 03:18:55 pm »
Perhaps obvious, but I thought I'd mention it.  A general matching process:

collect M measurement points  for all N devices

compute sum(k) | Pik - Pjk |  for i != j for the N**2-N combinations and the M measurements

sort on increasing sum, i and j and keep the first i in the list

This can be refined by including measurements at multiple temperatures,  measuring  noise figure and by restricting the measurements used for the sum to the desired operating conditions.  Collecting a full set of curves for each device will let you match or select the best device from inventory without remeasuring.

And yeah, I'm afraid I'm a bit NF obsessed as I missed out on getting some NOS very low noise figure JFETS  and many of the best are no longer made.

Edit:  Sorry about that.  I added the bounds N & M at the last minute.   It's just the calculation of the least summed absolute error followed by brute force selection of the optimal matches.  I was actually trying to work out the equations for heat transfer and temperature for TEC modules when this strayed into my head.  The TEC problem involves an exponential with a negative exponent, but I still haven't figure out how you get there from the information in the datasheet.  I think it's time to pull my Diff Eq book off the shelf and give myself a refresher.  I'd hoped that I would recognize the solution, but it's just been too long.

« Last Edit: May 05, 2018, 04:37:13 pm by rhb »
 

Offline Cerebus

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Re: FET selection process for precision circuits?
« Reply #30 on: May 05, 2018, 03:56:08 pm »
A general matching process:

collect M measurement points  for all N devices

compute sum(k) | Mik - Mjk |  for i != j for the N**2-N combinations and the M measurements

sort on increasing sum, i and j and keep the first i in the list

I have read that three times and I am still clueless as to what algorithm you are trying to describe. You define 'M' as the (scalar) number of measurement points and then start talking about either "Mik -  Mjk" or "M[i,j] - M[j,k]". As K9 would say "Does not compute, Master!".
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