HP3458 - Anybody have any oscillograms showing integrator timing?

[Cerebus]

Does anyone have any 'scope shots of an HP3458 showing the ADC integrator output during runup?

I'm trying to find precise timing information for the switching between the plus-zero, minus-zero and run-up slopes. While there's a lot of information, particularly in the HP Journal articles, on the 'shape' of these waveforms I can't find any timings for them. I'm just trying to tie together all the timings provided in the available literature for the various cycles, settling times, slew rates etcetera.

[Kleinstein]

I think TiN had a few scope traces in the thread about the repair of his first drifty (bad U180) 3458.

[Cerebus]

I'll go and look...

[carl_lab]

See HP Journal 1989-04, page 8-14:
http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1989-04.pdf

[Cerebus]

Found a couple of oscillograms in the middle of that monster thread of TiN's that provided the missing data.

For the record, here are the conclusions.

The basic ADC cycle time is 1.6us (32 clocks at 20 MHz). This cycle is in two parts 1.4us is the current balancing phase and 200ns is where a 'zero' balancing slope is applied (alternating between all balancing current sources off, or both positive and negative sources on together effectively injecting zero current again).

[Cerebus]

See HP Journal 1989-04, page 8-14:
http://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1989-04.pdf

Thanks for trying to help, but I believe that I'd made it pretty clear in the original post that what I was looking for wasn't there:

While there's a lot of information, particularly in the HP Journal articles, on the 'shape' of these waveforms I can't find any timings for them.

[carl_lab]

Oh, sorry, I should better read instead of quick scanning...

[Kleinstein]

The ADC of the 3458 to a certain point resembles the Landsburg ADC. It looks complicated but it is still a rather simple way to control the integrate phase. There was even an old (before the ICL7106/7) chips set for lower resolution (e.g. 4.5 digit ?) DMMs to use this method. The more special thing in the 3458 is the disintegrate phase at the end and the speed and precision parts used.
Some information on this type of ADC is available here:
https://dspace.mit.edu/handle/1721.1/84880

[Cerebus]

The ADC of the 3458 to a certain point resembles the Landsburg ADC. It looks complicated but it is still a rather simple way to control the integrate phase. There was even an old (before the ICL7106/7) chips set for lower resolution (e.g. 4.5 digit ?) DMMs to use this method. The more special thing in the 3458 is the disintegrate phase at the end and the speed and precision parts used.
Some information on this type of ADC is available here:
https://dspace.mit.edu/handle/1721.1/84880

The Multislope II ADCs in the HP 3458A, 3457A, 3467A and 3468A are all the same in basic principle, differing only in timings and the precision of certain critical components. The odd thing is that the service manuals for the latter three all have detailed timings available whereas the 3458 ADC, which gets an in detail expository article in the HP Journal, doesn't have published timings.

They all use the Landsburg 'trick' of fixing the number of current steering switch transitions, but they use a neutral 'no-current' phase whereas Landsburg used an injection of the opposite current to the one used for the main cycle. The advantage of the HP method is (1) you don't have to make a decision on what polarity you need to inject on a given cycle and (2) you don't have to account for that injection in your ADC count of balancing charge accumulated.