Impact of Frequency Division on Phase Noise

[Clemgill]

Hi,
Newby question... Hoping this is the right section to post(?)
Need to divide reference oscillator frequency by factors D=32 to 256
Trying to understand the impact of such division of the stability of the signal.
Reduces noise or increases noise ?
I have found very few references, some say it reduces (by sqrt(D)) without clear justification...
Others that say it adds noise...
I made some tests that show at least no impact or slight degradation of phase noise.
Thanks to point me at discussions / references of the matter if you know any.
Best,
Gilles.

[Kleinstein]

It depends on the divider and the way the phase noise is measured / defined.

At low noise levels just the divider can add noise from the gates, just like a simple flipflop. How much this is depends on the internal configuration: a simple ripple counter would produce more noise (the steps add up) than a synchronous counter which could get close the the noise of 1 flip flop.

The other point is principle loss in phase information by essentially throwing away most of the transitions. This often gives a factor sqrt(D). If the phase/frequency noise measure is relative to the carrier this improves the number by the factor D.

[Clemgill]

Hi,
Thanks for your reply.

Setup:
Input signal F=5.124Mhz sinus from a reasonably stable generator (ADEV # 1E-10)
Frequency divider using PIC12F675 (PICDIV like) with D = 32, 64, 256 and 1024
Input Sinus -> capacitor -> centering resistances -> fed as the PIC clock
ADEV measured with HP53132A (option 10, high stability oscillator) in Frequency mode -> GPIB -> Timelab.

Results to date (ADEV):
All F/D curves start above F curve and reconnect to it around tau=500sec.
Nothing "under" : so no improvement... no "D" or "sqrt(D)" improvement factors (actually something like the opposite)

Best,
Gilles.

[tggzzz]

The PIC12F675 MCU will be internally noisy due to all the processing (etc) activities occurring inside it. I would expect such noise to be coupled into the internal divider. Hence you may well be measuring the noise of the MCU, not the oscillator.

There's a reason RF test equipment is heavy: lots of internal metal shielding to keep noise from one part from affecting another part

[Clemgill]

The PIC is clocked by the signal to divide and just runs a delay loop + XOR to invert the output pin which produces the divided signal. Nothing else. I compared with a traditional ripple counting divider (CD4060) and the PIC is actually a bit quieter.
Doesn’t seem to be the root cause...
Thanks,
Gilles.

[jpb]

This is something I'm interested in as well.

From what I've read, I've not yet got practical experience, if the the delays through the divider are less than one period (so there isn't a danger of slipping a cycle if delays vary) then a final D type flip-flop stage reduces the added jitter (phase noise) to that of the final flip flop. That is the divided clock connects to the D input while the original clock goes to the clock of flip-flop.

It is easier to think in terms of jitter for a digital approach (though jitter and phase noise are related of course). If the last flip flop was perfect then the jitter would be jitter of the clock cycles when the data makes a transition so the same as the higher frequency signal (clock) except your only sampling every Nth cycle. As a fraction of T it is only 1/N as big. Of course the flip-flop will add something.

The thoughts I've had for the circuit I'm working on is to use a low phase noise buffer (LTC6957) which has 2 cmos outputs:

https://www.analog.com/media/en/technical-documentation/product-selector-card/2pb_6957.pdf

one output is divided down and the other clocks the last buffer flip-flop on the output.

The division is done by 4 bit synchronous counters. This is rather old-fashioned but it does at least make the delays well defined.

[David Hess]

The PIC is clocked by the signal to divide and just runs a delay loop + XOR to invert the output pin which produces the divided signal. Nothing else. I compared with a traditional ripple counting divider (CD4060) and the PIC is actually a bit quieter.

Internally the PIC has its own set of dividers which drive its state machines and logic.  The only thing distinguishing it from an 8-bit CISC microcontrollers of old (1) is a 2 stage pipeline producing a throughput of 1 instruction per cycle but each cycle is four oscillator cycles divided into a four phase clock just like microcontrollers of old.

The same solution for the asynchronous counter will work; add an external D flip-flop to reclock the output from the PIC and reduce the jitter to that from one flip-flop.  For extra credit, power the flip-flop from a separate low noise regulated supply because single ended logic has no power supply rejection.  Or use a flip-flop based on differential logic like ECL or I suppose made from fast differential comparators. (2)  There are also fascinating ways to make analog frequency dividers if you want to avoid the problems with logic.

(1) Just like an old CISC processor, the PIC uses microcode.  Just ask Microchip's lawyers.

(2) Unlike slow differential comparators like the 339/393, fast comparators like the 311 and anything faster use clamping to prevent storage time which reduces jitter.  This also means that schottky clamped TTL (LS, S, AS, FAST, whatever) or CMOS should be used instead of standard TTL (standard TTL, L, H) which suffers from saturation.

[Clemgill]

Excellent !
Would you have a recommendation for an appropriate D flip-flop reference ?
Also any relevant schematic also would be more than welcomed. I need to try this...

I found some good read on division + noise + jitter. Basically the phase noise would be divided by D but not the phase Jitter.
Moreovever there is an "aliasing" phenomenon - intrinsically induced by division - that adds noise with large division factor. I don't really understand that and need to further digest...

More soon,
Gilles. 

[Kleinstein]

A good flip-flop would be 74AC74.

The aliasing could come from the very high frequency jitter (frequencies higher than half the output frequency after the divider) that comes back to the low frequency region. Often this is not a problem, as the phase noise often has a significant 1/f part and the fast variations are thus often not that relevant.  Just from intuition I would expect it become a problem if the division is by more than the quality factor of the resonator in the oscillator.

[Clemgill]

Please take a look at the following paper :
https://www.silabs.com/community/blog.entry.html/2017/10/23/timing_101_the_case-uPOH
The author seems to get into aliasing with D as low as low as 8 ...
I am starting at D=32.