To add the fine ADC there are 2 options. One is using precision resistors, the one already at the DAC and another to add the fine part. With some 0.1% accuracy one could get some 8 bit accuracy for the fine part. So the fine part could offer an extra 8 Bit (maybe 9 or 10 at best ) bit resolution. Here it would not even need overlap. The divider only needs to be accurate to the full scale of the fine DAC, not to the full resolution.
The resistors need to be good quality, but no absolute need for a extra precision divider.
Especially with a little more resolution from the coarse part and less from the fine part, the resistors get less critical. Modern µCs can be a bit faster than the old days discrete logic and thus get a slightly high PWM base clock.
The alternative might be to not assume an accurate resistor ratio, but do a kind of internal cal cycle. In this case one would need some overlap, so that the fine ADC would cover some +-2 coarse steps. For the adjustment one would use different combinations to get the zero. From the measured near zero cases one would get a high resolution (e.g. 0.01% range) for the scale ratio between the coarse and fine steps. For the adjustment it helps to have a few overlapping steps, as one would get the fine steps corresponding to some 2,3 or 4 coarse steps and thus some extra resolution. I would expect the adjustment only to be needed rather infrequently, so it does not matter if it takes quite some times.
However the step ratio would likely not be a nice integer ratio like 1 coarse step corresponds to 1024 fine steps, but an arbitray number like 5123.6 fine steps to a coarse one. So when setting a DAC value, there will be rounding errors, though very small. When setting a fixed voltage, one would have that rounding problem anyway, as the steps would not correspond exactly µVs. With the measured ratio it is two scales with some odd size (e.g. 120.6 µV and 0.068 µV). The rounding problem is similar, maybe slight less as the steps can be smaller.
For the offset, I dont think that one would need an analog adjustment. It would be more like a rather crude but fixed offset to make sure one can reach the zero and a little below. The exact numerical zero reading would be corrected numerically by adding to the DAC setting.
A ready made DAC chip like the MCP4921 could in theory be an alternative to a PWM DAC for the fine part. But with the filter already there PWM is easy for the fine part and 12 Bit is easy, even if a simple circuit. In the old days one might have used an DAC to change the fine scale setting to get exactly 1024 fine steps to a coarse step, but today I would prefer the numerical way.
To speed the adjustment procedure and maybe add some resolution it helps if the zero detection it not just a comparator, but a high gain amplifier and an ADC, even if only some 8 bit. So the µC internal ADC should be good enough. It's a little like a Null-meter - low gain accuracy, but high amplification, low noise to detect even small deviations.
A single super high resolution PWM channel is possible too and simplifies the math. The delays from switching are not a special problem here - these only limit the use of the very extreme ends (like < 0.1% or > 99.8%), but this also applies to lower resolution. The coarse DAC needs to be precise to the full resolution anyway, so the demands are the same. There are 2 small downsides to those high clocked µCs: one is they tend to use a PLL clock an this can produce extra jitter that might be visible as extra noise. The other is that those higher speed µCs tend to produce more EMI problems, that might end up as extra offsets / noise somewhere. To avoid interactions, e.g. via ground currents the µC creating the PWM should not do much else during use. So even using the ADCs might already be too much.
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