This dead time is the time when essentially no current flows from the reference. The jitter looks like just steps of the ADC clock (seems to be 5 MHz). So it does not look critical, it's about what I expect: mainly one of two values with what looks like a single event of one more off. So far the switching looks OK.
If in a socket, one could try replacing U202 (LM301), as noise from this OP also enters ADC performance.
I would also consider adding local decoupling at the supply of OP IC201 - at least the plan I found does not have it (may be a note somewhere ?), which is a little strange.
Ok, I didn't save this picture the first time, because I also thought it should be ok. After your post in you said 100ns could be crucial I saved a picture. Ok, PWM is also fine..
I already installed a 100nF ceramics and a 2.2µF MKS on IC201, that doesn't changed anything.
There ist not much left. IC202 isn't in a socket, but if I found a LM301 in my lab I will replace it. Perhaps I should also try to replace the comparators (IC203 and IC204).
Might it be the case that a leaky integration capacitor cause this problems? I saw a huge offset an much more noise after cleaning the FET soldering, since some IPA went under IC201. It vanished after drying with a hair dryer.